Introduction to the CPM4 - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.4 English

The integrated block for PCIe® Rev. 4.0 with DMA and CCIX Rev. 1.0 (CPM4) is shown in the following figure.

Figure 1. CPM4 Sub-Block for PCIe Function (CPM4 PCIE)

CPM Components

The CPM includes multiple IP cores:
Controllers for PCIe
The CPM contains two instances of the AMD controller for PCIe, PCIe Controller 0 and PCIe Controller 1. Both controllers can have CCIX capabilities. However, only PCIe Controller 0 is capable of acting as an AXI bridge and as a DMA master. The controllers interface with the GTs through the XPIPE interface.
Coherent Mesh Network
The CPM has a Coherent Mesh Network (CMN) (not shown) that forms the cache coherent interconnect block in the CPM that is based on the Arm® CMN600 IP. There are two instances of L2 cache and CHI PL Interface (CPI) blocks in the CPM (also not shown).
DMA / AXI Bridge
CPM Controller 0 has a hardened DMA/AXI Bridge core. CPM Controller 1 does not have a hardened DMA core, but you can have a soft DMA/Bridge for Controller 1. The CPM Controller 0 has two possible direct memory access (DMA) IP cores. DMA Subsystem for PCIe (XDMA) and Queue DMA Subsystem for PCIe (QDMA). The DMA cores are used for data transfer between the programmable logic (PL) to the host, and from the host to PL. The DMA cores can also transfer data between the host and the Network-on-Chip (NoC), which provides high bandwidth to other NoC ports including the available DDR memory controllers (DDRMC). The CPM has an AXI Bridge Subsystem for PCIe (AXI Bridge) IP for AXI-to-host communication.

The CPM includes a clock/reset block that houses a phase-locked loop (PLL) and clock dividers. The CPM also includes the system-on-a-chip (SoC) debug component for transaction-level debug. Several APB and AXI interfaces are used between blocks in the CPM for configuration.

DMA Data Transfers

DMA transfers can be categorized into two different datapaths.

Data path from CPM to NoC to PL
All AXI4 signals are connected from the DMA to the AXI interconnect. These signals are then routed to the Non-Coherent interconnect in the CPM block. They then connect to the PS interconnect and the NoC. From the NoC, the signal can be directed to any block (DDR or block RAM) based on the user design. The figure below shows the datapath to NoC in red.
Data path from CPM directly to PL
All AXI4-Stream signals and other sideband signals, like clock and reset, are routed directly to the PL. The figure below shows the data path to the PL in green.
Figure 2. DMA Data Paths