| Port Name | I/O | Description |
|---|---|---|
| dma0_m_axis_h2c_tdata [AXI_DATA_WIDTH-1:0] |
O | Data output for H2C AXI4-Stream. |
| dma0_m_axis_h2c_par [AXI_DATA_WIDTH/8-1 : 0] |
O |
Odd parity calculated bit-per-byte over dma0_m_axis_h2c_tdata. dma0_m_axis_h2c_dpar[0] is parity calculated over dma0_m_axis_h2c_tdata[7:0]. dma0_m_axis_h2c_dpar[1] is parity calculated over dma0_m_axis_h2c_tdata[15:8], and so on. |
| dma0_m_axis_h2c_tuser_qid[10:0] | O | Queue ID |
| dma0_m_axis_h2c_tuser_port_id[2:0] | O | Port ID |
| dma0_m_axis_h2c_err | O | If set, indicates the packet has an error. The error could be coming from the PCIe, or the QDMA might have encountered a double bit error. |
| dma0_m_axis_h2c_mdata[31:0] | O | Metadata In internal mode, QDMA passes the lower 32 bits of the H2C AXI4-Stream descriptor on this field. |
| dma0_m_axis_h2c_mty[5:0] | O | The number of bytes that are invalid on the last beat of the transaction. This field is 0 for a 64B transfer. |
| dma0_m_axis_h2c_zero_byte | O | When set, it indicates that the current beat is an empty beat (zero bytes are being transferred). |
| dma0_m_axis_h2c_tvalid | O | Valid |
| dma0_m_axis_h2c_tlast | O | Indicates that this is the last cycle of the packet transfer. |
| dma0_m_axis_h2c_tready | I | Ready |