- Engineering Silicon (ES) is not supported for VC1902, VC1802, and
VM1802 devices. Only production silicon is supported for these devices.
-
PCIe features incompatible with
Tandem Configuration:
-
PCIe Extended
Configuration Space as this requires PL logic.
- QDMA multi-function is not supported. This feature uses PL
mailbox which is probed during driver load.
- Stage 1 and stage 2 PDI images must remain linked. If you update one,
update the other to ensure both stages have been generated from the same implemented
design.
- Do not reload the same or a new stage 2 image on the fly. Isolation
circuitry on the periphery of the CPM is designed to ensure safe operation of the
PCI Express endpoints prior to the rest of the
device becoming active. Upon stage 2 completion, this isolation is released and it
is not re-enabled for a dynamic reload of the stage 2 image.
- For the Versal architecture, CPM
Tandem PROM configuration can be used with post configuration flash update. This is
different from previous (UltraScale+ and older) architectures that did not support
Tandem PROM post configuration flash update. Given the lack of dual-mode
configuration pins, there is no PERSIST requirement to keep a configuration port
active.
- At this point there is no Tandem with Field Updates predefined use
case. You can create a Tandem + DFX solution noted above where both features are
enabled in the same design, but creation of the design hierarchy and floorplan as
well as insertion of any decoupling logic are the responsibility of the designer.
The dynamic (DFX) portion of the solution would be limited to programmable logic and
NoC resources, and not parts of the Scalar Engines (processors).
- No support is planned for Tandem Configuration for PL-based PCIe sites. The complexity and inefficiency of such a
solution in Versal device makes it very
difficult to meet the 120 ms goal for Tandem PROM and impossible for Tandem PCIe. If compliant link training is a fundamental
requirement, be sure to use a device with the CPM and enable the Tandem feature
within CIPS customization.
- When debug within a Tandem design,
debug_nets.ltx file should only be included after stage2 is
loaded. Loading the debug_nets.ltx file when only stage1 is
present, it causes tool errors when trying to access the debug cores that exist as
part of the stage2 design.