| Port Name | I/O | Description |
|---|---|---|
| dma<n>_m_axis_h2c_tdata [AXI_DATA_WIDTH-1:0] |
O | Data output for H2C AXI4-Stream. |
| dma<n>_m_axis_h2c_tcrc [31:0] |
O |
32-bit CRC value for that beat. IEEE 802.3 CRC-32 Polynomial |
| dma<n>_m_axis_h2c_qid[10:0] | O | Queue ID |
| dma<n>_m_axis_h2c_port_id[2:0] | O | Port ID |
| dma<n>_m_axis_h2c_err | O | If set, indicates the packet has an error. The error could
come from the PCIe, or the error could be in the DMA transfer.
AMD recommends that you look at the error registers and
context for details. When the DMA first detects the error, the error bit will be set to 1. And the error bit will be set for the remainder of that packet. The error bit will be reset to 0 for the next packet if there are no errors in that packet. |
| dma<n>_m_axis_h2c_mdata[31:0] | O | Metadata In internal mode, QDMA passes the lower 32 bits of the H2C AXI4-Stream descriptor on this field. |
| dma<n>_m_axis_h2c_mty[5:0] | O | The number of bytes that are invalid on the last beat of the transaction. This field is 0 for a 64B transfer. |
| dma<n>_m_axis_h2c_zero_byte | O | When set, it indicates that the current beat is an empty beat (zero bytes are being transferred). |
| dma<n>_m_axis_h2c_tvalid | O | Valid |
| dma<n>_m_axis_h2c_tlast | O | Indicates that this is the last cycle of the packet transfer |
| dma<n>_m_axis_h2c_tready | I | Ready |