This appendix includes guidance on Interrupt Request (IRQ) pins routing and programming for CPM4. Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express provides three independent IRQ pins routed to the Programmable Logic (PL) region as well as three independent IRQ pins routed to the hardened Processing System (PS) region. These IRQ pins are shared between the two PCIe controllers and all CPM4 use modes and can be programmed by user to route one or many Interrupt sources.
The three IRQ pins routed to the PL region are named
cpm_misc_irq, cpm_cor_irq, and
cpm_uncor_irq and are visible in the Vivado Block
Diagram (BD) canvas at the Versal CIPS IP boundary. Although, the IRQ
pins are named as miscellaneous, correctable, and uncorrectable respectively, they
function identically from each other and have the same list of Interrupt source to
select from. Therefore, you can assume these IRQ pins as three separate general purpose
IRQ pins.
The three IRQ pins routed to the PS regions are named similarly however they are not visible in the Vivado BD canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of Interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.
There are many interrupt sources to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express is only available on Controller 0. This appendix will provide some use cases example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the Interrupt Request.
Example: Generate Interrupt Request for Hot Reset
In this example, you generate interrupt whenever the hot reset is received for
PCIe0 controller. You route an interrupt generated from the PCIe0 controller to the
PS region. You use the cpm_misc_irq pin as an example, but any
other pins can also be used. Note that in this particular example, you use the
pcie_local_event interrupt line at the CPM_SLCR mux level which
is driven by XDMA_REG.INT_DEC register. A high level block diagram of the interrupt
routing is shown in the following diagram:
- Register programming to enable Hot Reset event interrupt
- The following register shall be programmed by you at runtime to enable the Interrupt:
- Interrupt service routine
- The following steps outlines the recommended procedure to service the interrupt request.
Example: Generate Interrupt Request for MSI Interrupt as Root Port
In this example, you will generate the interrupt whenever MSI vector 0
interrupt is received for PCIe0 controller. You will route the interrupt generated
from PCIe0 controller to the PS region. You will use the
cpm_misc_irq pin as an example, but any other pins can also be
used. Note that in this particular example, you will use the
pcie_msi0 interrupt line at the CPM_SLCR mux level which is
driven by XDMA_REG.MSI_DEC_31_0 register. A high level block diagram of the
interrupt routing is shown in the following diagram:
- Register programming to enable MSI vector 0 event interrupt
- The following register shall be programmed by you at runtime to enable the interrupt:
- Interrupt service routine
- The following steps outlines the recommended procedure to service the interrupt request: