Interrupt Request (IRQ) Routing and Programming for CPM4 - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-05-30
Version
3.4 English

This appendix includes guidance on Interrupt Request (IRQ) pins routing and programming for CPM4. Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express provides three independent IRQ pins routed to the Programmable Logic (PL) region as well as three independent IRQ pins routed to the hardened Processing System (PS) region. These IRQ pins are shared between the two PCIE controllers and all CPM4 use modes and can be programmed by user to route one or many Interrupt sources.

The three IRQ pins routed to the PL region are named cpm_misc_irq, cpm_cor_irq, and cpm_uncor_irq and are visible in the Vivado Block Diagram (BD) canvas at the Versal CIPS IP boundary. Although, the IRQ pins are named as miscellaneous, correctable, and uncorrectable respectively, they function identically from each other and have the same list of Interrupt source to select from. Therefore, you can assume these IRQ pins as three separate general purpose IRQ pins.

The three IRQ pins routed to the PS regions are named similarly however they are not visible in the Vivado BD canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of Interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.

There are many interrupt sources to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express is only available on Controller 0. This appendix will provide some use cases example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the Interrupt Request.

Example: Generate Interrupt Request for Hot Reset

In this example, you generate interrupt whenever the hot reset is received for PCIE0 controller. You route an interrupt generated from the PCIE0 controller to the PS region. You use the cpm_misc_irq pin as an example, but any other pins can also be used. Note that in this particular example, you use the pcie_local_event interrupt line at the CPM_SLCR mux level which is driven by XDMA_REG.INT_DEC register. A high level block diagram of the interrupt routing is shown in the following diagram:

Figure 1. Interrupt Routing Diagram

Register programming to enable Hot Reset event interrupt
The following register shall be programmed by you at runtime to enable the Interrupt:
  • For PCIE0 controller
    1. CPM_SLCR.PS_MISC_IR_ENABLE set to 0x2 to select "pcie_local_event"
    2. Read to confirm that CPM_SLCR.PS_MISC_IR_MASK is cleared for bit[1] "pcie_local_event"
    3. XDMA_REG.INT_MASK set to 0x8 to select "hot_reset"
    4. Read to confirm that XDMA_REG.INT_MASK is set for bit[3] "hot_reset"
Interrupt service routine
The following steps outlines the recommended procedure to service the interrupt request.
  • For PCIE0 controller
    1. Upon receiving interrupt, read CPM_SLCR.PS_MISC_IR_STATUS to confirm bit[1] "pcie_local_event" is asserted
    2. CPM_SLCR.PS_MISC_IR_DISABLE set to 0x2 to temporarily mask "pcie_local_event" so further interrupt is not received while existing interrupt is being serviced
    3. Read XDMA_REG.INT_DEC to confirm bit [3] "hot_reset" is asserted.
    4. XDMA_REG.INT_MASK set to 0x0 to temporarily mask "hot_reset"
    5. Execute user-defined task for servicing Hot Reset event
    6. XDMA_REG.INT_DEC set to 0x8 to clear "hot_reset"
    7. CPM_SLCR.PS_MISC_IR_STATUS set to 0x2 to clear "pcie_local_event"
    8. Re-enable / unmask Hot Reset event interrupt source by programming the CPM_SLCR.PS_MISC_IR_ENABLE and XDMA_REG.INT_MASK registers

Example: Generate Interrupt Request for MSI Interrupt as Root Port

In this example, you will generate the interrupt whenever MSI vector 0 interrupt is received for PCIE0 controller. You will route the interrupt generated from PCIE0 controller to the PS region. You will use the cpm_misc_irq pin as an example, but any other pins can also be used. Note that in this particular example, you will use the pcie_msi0 interrupt line at the CPM_SLCR mux level which is driven by XDMA_REG.MSI_DEC_31_0 register. A high level block diagram of the interrupt routing is shown in the following diagram:

Figure 2. Interrupt Routing Diagram

Register programming to enable MSI vector 0 event interrupt
The following register shall be programmed by you at runtime to enable the interrupt:
  • For PCIE0 controller
    1. CPM_SLCR.PS_MISC_IR_ENABLE set to 0x4 to select "pcie_msi0"
    2. Read to confirm that CPM_SLCR.PS_MISC_IR_MASK is cleared for bit[2] "pcie_msi0"
    3. XDMA_REG.MSI_MASK_31_0 set to 0x1 to select "MSI vector 0"
    4. Read to confirm that XDMA_REG.MSI_MASK_31_0 is set for bit[0] "MSI vector 0"
Interrupt service routine
The following steps outlines the recommended procedure to service the interrupt request:
  • For PCIE0 controller
    1. Upon receiving interrupt, read CPM_SLCR.PS_MISC_IR_STATUS to confirm bit[2] "pcie_msi0" is asserted
    2. CPM_SLCR.PS_MISC_IR_DISABLE set to 0x4 to temporarily mask "pcie_msi0" so further interrupt is not received while existing interrupt is being serviced
    3. Read XDMA_REG.MSI_DEC_31_0 to confirm bit [0] "MSI vector 0" is asserted.
    4. XDMA_REG.MSI_MASK_31_0 set to 0x0 to temporarily mask "MSI vector 0"
    5. Execute user-defined task for servicing MSI interrupt
    6. XDMA_REG.MSI_DEC_31_0 set to 0x1 to clear "MSI vector 0"
    7. CPM_SLCR.PS_MISC_IR_STATUS set to 0x4 to clear "pcie_msi0"
    8. Re-enable / unmask FLR event interrupt source by programming the CPM_SLCR.PS_MISC_IR_ENABLE and XDMA_REG.MSI_MASK_31_0 registers