Revision History - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-11-22
Version
3.4 English

The following table shows the revision history for this document.

Section Revision Summary
11/22/2024 Version 3.4
Resets Updated section.
Segmented Configuration Added section.
Using the Provided Software and Drivers Added a note.
C2H Stream Modes Updated section.
Enable the Tandem Configuration Solution Updated section.
Completion Engine Added a note.
QDMA Performance Optimization Updated section.
Reset in a Root Port Mode Added new section.
Deliver Programming Images to Silicon Updated section.
AXI to PCIe BARs Updated section.
Customizable Example Design (CED) Updated section.
NoC Ports Updated section.
QDMA Descriptor Bypass Input Ports Added figures.
QDMA Descriptor Bypass Output Ports Added figures.
Limitations Updated section.
05/30/2024 Version 3.4
Terminology Updated terminology.
Supported Devices Updated Tandem Configuration Supported Devices table.
Enable the Tandem Configuration Solution Updated figures.
Design Version Compatibility Checks Added new section.
Tandem PCIe and DFX Configurable Example Design Updated section.
Function Map Table Updated for FMAP programming in mailbox IP.
Limitations Updated.
MSIX Interrupt Options Added new section.
11/20/2023 Version 3.4
CPM4_QDMA_Gen4x8_MM_ST_Design Added new section.
Example Design Registers Added new section.
CED Generation Steps Added new section.
CPM4_QDMA_Gen4x8_MM_ST_Performance_Design Added new section.
Versal_CPM_QDMA_EP_Simulation_Design Added new section.
Versal_CPM_Bridge RP_Design Added new section.
CPM5_QDMA_Gen4x8_MM_ST_Design Added new section.
CPM5_QDMA_Gen5x8_MM_Performance_Design Added new section.
CPM5_QDMA_Gen4x8_ST_Performance_Design Added new section.
CPM5_QDMA_Dual_Gen4x8_MM_ST_Design Added new section.
Versal_CPM_QDMA_EP_Simulation_Design Added new section.
Versal_CPM_Bridge RP_Design Added new section.
CPM5_QDMA_Gen5x8_ST_Performance_Design Added new section.
CPM5_QDMA_Dual_Gen5x8_ST_Performance_Design Added new section.
Interrupt Request (IRQ) Routing and Programming for CPM4 Added new section.
Interrupt Request (IRQ) Routing and Programming for CPM5 Added new section.
Supported Devices Added new section.
Tandem + DFX Added new section.
QDMA Performance Optimization Updated.
Enable the Tandem Configuration Solution Updated.
AXI Bridge Subsystem Added new figure.
AXI Bridge Subsystem Added new figures.
05/16/2023 Version 3.3
General updates Entire document.
Data Bandwidth and Performance Tuning Updated.
Enable the Tandem Configuration Solution Added a note.
Tandem PCIe and DFX Configurable Example Design Added new section.
Known Issues and Limitations Updated.
Simulation Added new section.
Customizable Example Design (CED) Added new chapter
QDMA Performance Optimization Added QDMA Performance Registers table.
User Interrupts Updated User Interrupts Port Descriptions table.
11/02/2022 Version 3.3
General updates Entire document.
Clocking Updated clock frequency.
Tandem Configuration Updated for clarification.
Master Bridge Updated for clarification.
Function Map Table Updated description.
Context Programming Updated context programming for CPM4.
Context Programming Updated context programming for CPM5.
06/15/2022 Version 3.0
General updates Entire document.
04/29/2022 Version 3.0
General updates Updated for Versal Premium adaptive SoC support.
12/17/2021 Version 3.0
General Update Updated for the CIPS IP v3.0.
Limitations Added known issues for the release.
QDMA Features and XDMA Features Added clarifying details regarding AXI4-Stream interface data rate support.
12/04/2020 Version 2.1
Initial release. N/A