CPM5 Mailbox IP - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2023-11-20
Version
3.4 English

You need to add a new IP from the IP catalog to instantiate pcie_qdma_mailox Mailbox IP. This IP is needed for function virtualization. pcie_qdma_mailbox IP should be connected to the versel_cips IP as shown in the following diagram:

Figure 1. CPM5 Mailbox Connection

Note: Mailbox ports are always connected to Mailbox IP. If Mailbox IP is not used, leave the port unconnected (floating). See the preceding figure for connection reference.

The following connections are related to the above example design. To connect the Mailbox IP, follow these steps:

  1. Add PCIe QDMA Mailbox IP. To do so:
    1. Configure the IP for the number of PFs (should be same as number of PFs selected in QDMA configuration).
    2. Configure the IP for the number of VFs in each PF (should be same as number of VFs selected in QDMA configuration).
    Note: It is important to match number PFs and VFs to the numbers configured in the QMDA IP. If not, the design will not work.
  2. Re-configure the NoC IP to add one extra AXI Master port. To do so:
    1. Assign one more AXI clock.
    2. In the Outputs tab, assign M02_AXI to aclk2.
    3. In the Connectivity tab, select the M02_AXI PL option for both S00_AXI and SS01_AXI ps_pcie.
  3. Add AXI SmartConnect IP.
    1. Configure the IP to have one master, one slave, one clock, and one reset.
Mailbox IP has two clocks and two resets as shown in the preceding figure. In this example, both the clocks are generated from the PMC block.
axi_aclk
Mailbox IP runs at 250 MHz, this clock is used internaly in the Mailbox IP.
ip_clk
Depending on the configuration, the PL might need to run at a higher frequency to satisfy the data throughput. For example, Gen5x8 PL need to run at 433 MHz to satisfy the data throughput. ip_clk should be connected to 433 MHz clock in this case.
ip_resetn
It is synchronous with ip_clk and it is derived from the CIPS IP.
axi_aresetn
It is synchronous with axi_aclk. Use pro_sys_reset IP to generate a reset synchronous to axi_aclk.
For some configurations, the PL clock's maximum speed is 250 MHz. For example, Gen3x16 and Gen4x8 configurations. The PL clock runs at 250 MHz and pcie_qdma_mailbox IP also runs at 250 MHz. In this case, connect ip_clk and axi_aclk clock and ip_resetn and axi_aresetn reset.

Follow the CPM5 Mailbox Connection figure to make the following connections:

  1. Connect M02_AXI interface to Smartconnect1, from Smartconnect1, connect M00_AXI to Mailbox IP.
  2. Connect dma0_usr_irq from CIPS IP to the Mailbox IP output.
  3. Connect dma0_usr_flr from CIPS IP to the Mailbox IP output.
  4. Make usr_flr and usr_irq interface in the Mailbox IP as external pins.
Note: Mailbox access can be steered to NoC0 or NoC1 port based on CIPS gui configuration. You should configure the NoC based on CIPS gui selection.