C2H Streaming Fatal Error Handling - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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  • QDMA_C2H_FATAL_ERR_STAT (0xAF8): The error status register of the C2H streaming fatal errors.
  • QDMA_C2H_FATAL_ERR_MASK (0xAFC): The error mask register. The SW can set the bit to enable the corresponding C2H fatal error to be sent to the C2H fatal error handling logic.
  • QDMA_C2H_FATAL_ERR_ENABLE (0xB00): This register enables two C2H streaming fatal error handling processes:
    Stop the data transfer by disabling the write request from the C2H DMA write engine by setting enable_wrq_dis bit [0] to 1.
    Invert the write payload parity on the data transfer by setting enable_wpl_par_inv bit [1] to 1.