C2H_COMPLETION_SIZE (0x050) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English
Table 1. C2H_COMPLETION_SIZE (0x050)
Bit Default Access Type Description
[31:13] 0 NA Reserved
[12] 0 RW Completion Type.

1'b1: NO_PLD_BUT_WAIT

1'b0: HAS PLD

[10:8] 0 RW s_axis_c2h_cmpt_ctrl_err_idx[2:0] Completion Error Bit Index.

3'b000: Selects 0th register.

3'b111: No error bit is reported.

[6:4] 0 RW s_axis_c2h_cmpt_ctrl_col_idx[2:0] Completion Color Bit Index.

3'b000: Selects 0th register.

3'b111: No color bit is reported.

[3] 0 RW s_axis_c2h_cmpt_ctrl_user_trig Completion user trigger
[1:0] 0 RW AXI4-Stream C2H completion data size.

00: 8 Bytes

01: 16 Bytes

10: 32 Bytes

11: 64 Bytes