| Port Name | I/O | Description |
|---|---|---|
| gt_refclk0_p/gt_refclk0_n | I | GT reference clock |
| pci_gt_txp/pci_gt_txn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | O | PCIe TX serial interface. |
| pci_gt_rxp/pci_gt_rxn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | I | PCIe RX serial interface. |
| pcie0_user_lnk_up | O | Output active-High identifies that the PCI Express core is linked up with a host device. |
| pcie0_user_clk | O | User clock out. PCIe derived clock output for all interface signals output/input to the QDMA. Use this clock to drive inputs and gate outputs from QDMA. |
| dma0_axi_aresetn | O | User reset out. AXI reset signal synchronous with the clock provided on the pcie0_user_clk output. This reset should drive all corresponding AXI Interconnect aresetn signals. |
| dma0_soft_resetn | I | Soft reset (active-Low). Use this port to assert reset and reset the DMA logic. This will reset only the DMA logic. User should assert and de-assert this port. |
All AXI interfaces are clocked out and in by the pcie0_user_clk signal. You are responsible for using pcie0_user_clk to drive all signals into the CPM.
pcie0_user_clk should be used to interface
with the CPM. In the user logic, any available clocks can be used.