Channel 0-3 DMA Status Interface - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2023-11-20
Version
3.4 English
Table 1. Channel 0-3 DMA Status Interface
Signal Name Direction Description
dma0_h2c_sts_x [7:0] O Status bits for each channel. Bit:

6: Control register 'Run' bit

5: IRQ event pending

4: Packet Done event (AXI4-Stream)

3: Descriptor Done event. Pulses for one cycle for each descriptor that is completed, regardless of the Descriptor.Completed field

2: Status register Descriptor_stop bit

1: Status register Descriptor_completed bit

0: Status register busy bit
dma0_c2h_sts_x [7:0] O Status bits for each channel. Bit:

6: Control register 'Run' bit

5: IRQ event pending

4: Packet Done event (AXI4-Stream)

3: Descriptor Done event. Pulses for one cycle for each descriptor that is completed, regardless of the Descriptor.Completed field

2: Status register Descriptor_stop bit

1: Status register Descriptor_completed bit

0: Status register busy bit
  1. _x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the dma0_c2h_sts_0 port, and for channel 1 use the dma0_c2h_sts_1 port.