QDMA_DMAP_SEL_CMPT_CIDX[2048] (0x640C) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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Table 1. QDMA_DMAP_SEL_CMPT_CIDX[2048] (0x640C)
Bit Default Access Type Field Description
[31:29] 0 NA Reserved Reserved
[28] 0 RW irq_en_wrb Interrupt arm. Set this bit to 1 for next interrupt generation.
[27] 0 RW en_sts_desc_wrb Enable Status Descriptor for CMPT
[26:24] 0 RW trigger_mode Interrupt and Status Descriptor Trigger Mode:

0x0: Disabled

0x1: Every

0x2: User_Count

0x3: User

0x4: User_Timer

0x5: User_Timer_Count

[23:20] 0 RW c2h_timer_cnt_index Index to QDMA_C2H_TIMER_CNT
[19:16] 0 RW c2h_count_threshhold Index to QDMA_C2H_CNT_TH
[15:0] 0 RW wrb_cidx CMPT Consumer Index (CIDX)