FLR Control/Status Register (0x42500) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-05-30
Version
3.4 English
Table 1. FLR Control/Status Register (0x42500)
Bit Default Access Type Field Description
[31:1] 0 NA Reserved Reserved
[0] 0 RW Flr_status Software write 1 to initiate the Function Level Reset (FLR) for the associated function. The field is kept asserted during the FLR process. After the FLR is done, the hardware de-asserts this field.