Simulation example designs are
listed in the configurable example design (CED). You can download the simulation example
design from the Vivado store Versal_CPM5_QDMA_Simultion_Design. The list of Versal
PCIe example designs are available here. Simulation design has a fixed configuration as
follows:
- Gen4x8
- AXI4 and AXI-ST
- 4 PF and 250 VF's
- Each Function with two BAR's. One for QDMA configuration space and one for Bypass access to PL.
- Descriptor bypass and Internal Mode
Following is the procedure to generate a CPM5 QDMA simulation design:
- Open Vivado and select Open Example Project option under Quick
Start.Note: In simulation, you might receive warnings from internal RAMs within the CPM5 block indicating that a write/read contention has occurred on a multi-port RAM. This is normal as the contention is resolved separately outside of the RAM blocks. These warnings can be safely ignored.
- From the Template options, select Versal CPM5 QDMA Simulation
Design under PCIe section. You can see the corresponding diagram
on the right-hand side description section. click
Next.
The Vivado wizard guides you through the board/part section. This example design is fixed to VPK120 board.
- Select the project name and directory and click Next to generate project.
- A new simulation project is displayed as shown below.
This project has cpm_qdma (EP design) and design_rp (root port model). And all the relevant files that are need for simulation.