Navigating Content by Design Process - 3.4 English

AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. You can access the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the Design Flow Assistant to better understand the design flows and find content that is specific to your intended design needs.

System and Solution Planning

Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:

• Introduction to the CPM4
  • Use Modes
• Introduction to the CPM5
  • Use Modes

Embedded Software Development

Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. Topics in this document that apply to this design process include:

• CPM4
  • QDMA Subsystem
    • Register Space
    • Application Software Development
  • AXI Bridge Subsystem
    • Register Space
  • XDMA Subsystem
    • Register Space
    • Application Software Development
• CPM5
  • QDMA Subsystem
    • Register Space
    • Application Software Development
  • AXI Bridge Subsystem
    • Register Space

Hardware, IP, and Platform Development​

Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the AMD Vivado™ timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

• CPM4
  • QDMA Subsystem: Lab1: QDMA AXI MM Interface to NoC and DDR
• • QDMA Subsystem: Lab2: QDMA AXI MM Interface to NoC and DDR with Mailbox
  • XDMA Subsystem: XDMA AXI MM Interface to NoC and DDR Lab
• CPM5
  • QDMA Subsystem: QDMA AXI MM Interface to NoC and DDR Lab