QDMA_PF_MAILBOX (0x42400) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.4 English
Table 1. QDMA_PF_MAILBOX (0x42400) Register Space
Register Address Description
Function Status Register (0x42400) 0x42400 Status bits
Function Command Register (0x42404) 0x42404 Command register bits
Function Interrupt Vector Register (0x42408) 0x42408 Interrupt vector register
Target Function Register (0x4240C) 0x4240C Target Function register
Function Interrupt Vector Register (0x42410) 0x42410 Interrupt Control Register
RTL Version Register (0x42414) 0x42414 RTL Version Register
PF Acknowledgment Registers (0x42420-0x4243C) 0x42420-0x2243C PF acknowledge
FLR Control/Status Register (0x42500) 0x42500 FLR control and status
Incoming Message Memory (0x42C00-0x42C7C) 0x42C00-0x42C7C Incoming message (128 bytes)
Outgoing Message Memory (0x43000-0x4307C) 0x43000-0x4307C Outgoing message (128 bytes)

Mailbox Addressing

PF addressing
Addr = PF_Bar_offset + CSR_addr
VF addressing
Addr = VF_Bar_offset + VF_Start_offset + VF_offset + CSR_addr