The size of a Completion (CMPT) Ring entry is 512-bits. This includes user defined data, an optional error bit, and an optional color bit. The user defined data has four size options: 8B, 16B, 32B and 64B. The bit locations of the optional error and color bits in the CMPT entry are configurable individually. This is done by specifying the locations of these fields using the AMD Vivado™ IDE IP customization options while compiling the QDMA. There are seven color bit location options and eight error bit location options. The location is specified as an offset from the LSB bit of the Completion entry.
When the user application drives a Completion packet into the QDMA, it provides a dma<n>_s_axis_cmpt_ctrl_col_idx[2:0] value and a
dma<n>_s_axis_cmpt_ctrl_err_idx[2:0] value
at the interface. These indices are used by the QDMA to use the correct locations of the color and error
bits. For example, if dma<n>_s_axis_cmpt_ctrl_col_idx[2:0] = 0 and dma<n>_s_axis_cmpt_ctrl_err_idx[2:0] = 1, then the
QDMA uses the C2H Stream Completion Color bits position option 0
for color location, and C2H Stream Completion Error
bits position option 1 for error location. An index of seven for
color or error signals implies that the DMA will not update the corresponding color
or error bits when Completion entry is updated (those fields are ignored). The C2H
Stream Completions bits options are set in the PCIe DMA Tab in the AMD Vivado™
IDE.
The error and color bit location values that are used at compile time are available for the software to read from the MMIO registers. There are seven registers for this purpose, QDMA_C2H_CMPT_FORMAT (0xBC4) to QDMA_GLBL_ERR_MASK (0x24C). Each of these registers holds one color and one error bit location.
- C2H Stream Completions bits option 0 for color bit location and option 0 for error bit location are available through the QDMA_C2H_CMPT_FORMAT_0 register.
- C2H Stream Completions bits option 1 for color bit location and option 1 for error bit location are available through the QDMA_C2H_CMPT_FORMAT_1 register.
- And so on.
Based on the CMPT data size selection (8, 16, 32 or 64 Bytes), the data in
s_axis_c2h_cmpt_tdata[511:0] signal is registered in the
completion entry as shown in the following table.
| Name | Size (Bits) | Index |
|---|---|---|
|
User-defined bits for 64 Bytes settings |
510-512 | Depending on whether there are color and error bits present. |
|
User-defined bits for 32 Bytes settings |
254-256 | Depending on whether there are color and error bits present. |
|
User-defined bits for 16 Bytes settings |
126-128 | Depending on whether there are color and error bits present. |
|
User-defined bits for 8 Bytes settings |
62-64 | Depending on whether there are color and error bits present. |
| Err | The Error bit location is defined by registers QDMA_C2H_CMPT_FORMAT_0
(0xBC4) to QDMA_C2H_CMPT_FORMAT_6 (0xBDC). These register show color
bit position that is user defined during IP generation. You can
index into this register based on input CMPT ports dma<n>_s_axis_c2h_cmpt_ctrl_err_idx[2:0]. You can
choose not to include err bit (index value 7). In such a case,
user-defined data takes up that space |
|
| Color | The Color bit location is defined by registers QDMA_C2H_CMPT_FORMAT_0
(0xBC4) to QDMA_C2H_CMPT_FORMAT_6 (0xBDC).These register show color
bit position that is user defined during IP generation. You can
index into this register based on input CMPT ports dma<n>_s_axis_c2h_cmpt_ctrl_col_idx[2:0]. If you do
not include a color bit (index value 7), the user-defined data takes
up that space. |