C2H Channel 0-3 AXI4-Stream Interface Signals - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID: PG347
Release Date: 2024-05-30
Version: 3.4 English

Table 1. C2H Channel 0-3 AXI4-Stream Interface Signals
Signal Name¹	Direction	Description
dma0_s_axis_c2h_x_tready	O	Assertion of this signal indicates that the DMA is ready to accept data. Data is transferred across the interface when dma0_s_axis_c2h_tready and dma0_s_axis_c2h_tvalid are asserted in the same cycle. If the DMA deasserts the signal when the valid signal is High, the user logic must keep the valid signal asserted until the ready signal is asserted.
dma0_s_axis_c2h_x_tlast	I	The user logic asserts this signal to indicate the end of the DMA packet.
dma0_s_axis_c2h_x_tdata [DATA_WIDTH-1:0]	I	Transmits data from the user logic to the DMA.
dma0_s_axis_x_tkeep [DATA_WIDTH/8-1:0]	I	tkeep must all be 1s for all cycles except when dma0_s_axis_c2h_x_tlastis asserted. The asserted tkeep bits need to be packed to the lsb, indicating contiguous data.
dma0_s_axis_c2h_x_tvalid	I	The user logic asserts this whenever it is driving valid data on dma0_s_axis_c2h_tdata.
dma0_s_axis_c2h_x_tuser [DATA_WIDTH/8-1:0]	I	Parity bits. This port is enabled only in Propagate Parity mode.
_x in the signal name changes based on the channel number 0, 1, 2, and 3. For example, for channel 0 use the dma0_m_axis_c2h_tready_0 port, and for channel 1 use the dma0_m_axis_c2h_tready_1 port.