CPM5_QDMA_Gen5x8_ST_Performance_Design - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-05-30
Version
3.4 English

CPM5 QDMA1 with Gen5x8 AXI4-Stream performance example design:

  • The design targets "xcvp1202-3HP-e-S" part and it supports synthesis and implementation flows
  • This design has CPM5 – QDMA1 enabled in Gen5x8, AXI4-Stream configuration as an End Point
  • Capable of demonstrating AXI-ST performance
  • Capable of performing in internal modes or cache bypass mode or in simple bypass mode
  • To enable the Simple bypass mode in the example design, you need to set the register offset 0x98 to 0x4
  • To change the data packet size on C2H direction, you need to set the example design register offset 0x90 to the desired value

Performance Example Design Simple Bypass Mode Flow

In this example design, QMDA configuration bar is set to BAR0. Performance example design can be controlled through AXI4-Lite bar which is BAR 0. Find out what is the bar offset for the QDMA configuration bar (BAR0) and AXI4-Lite bar (BAR2).

  1. Put example design in pause mode. Set offset 0x8 bit [30] to 1, all other bit values should not be changed
  2. Set the example design in simple bypass mode. Set offset 0x98 to 0x4
  3. Set the desired packet size. Set offset 0x90 to the desired value
  4. Enable and start the data transfer from the host application/driver

    At this time no data transfer happens as the example design is paused.

  5. Now you need to fetch the prefetch tag from QDMA IP (configuration bar)
    • Write 0 to QDMA configuration bar (BAR0) offset 0x1048. Write offset 0x1408 with value 0x0
    • Read prefetch tag from QDMA configuration bar (BAR0). Read offset 0x140C
    • You need to write that tag value to the example design (BAR2). Write tag value to offset 0x24
  6. After the prefetch tag exchange, you can release the example design. Set offset 0x8 bit [30] to 0. All other bits should not be changed
  7. You can now see the data transfer from example design to host