Software Descriptor Context Structure (0x0 C2H and 0x1 H2C) - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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The descriptor context is used by the descriptor engine.

Table 1. Software Descriptor Context Structure Definition
Bit Bit Width Field Name Description
[255:148] 108 reserved Reserved. Set to 0s.
[147:144] 4 host_id host_id is index into the host_profile registers to determine the steering for AXI4 MM transfers.
[143:140] 4 reserved Reserved. Set to 0s.
[139] 1 int_aggr If set, interrupts will be aggregated in interrupt ring.
[138:128] [10:0] vec MSI-X vector used for interrupts for direct interrupt or interrupt aggregation entry for aggregated interrupts.
[127:64] 64 dsc_base 4K aligned base address of descriptor ring.
[63] 1 is_mm

This field determines if the queue is Memory Mapped or not. If this field is set, the descriptors will be delivered to associated H2C or C2H MM engine.

1: Memory Mapped

0: Stream

[62] 1 mrkr_dis

If set, disables the marker response in internal mode.

Not applicable for C2H ST.

[61] 1 irq_req

Interrupt due to error waiting to be sent (waiting for irq_arm). This bit should be cleared when the queue context is initialized.

Not applicable for C2H ST.

[60] 1 err_wb_sent

A writeback/interrupt was sent for an error. Once this bit is set no more writebacks or interrupts will be sent for the queue. This bit should be cleared when the queue context is initialized.

Not applicable for C2H ST.

[59:58] 2 err

Error status.

Bit[1] dma – An error occurred during DMA operation. Check engine status registers.

Bit[0] dsc – An error occurred during descriptor fetch or update. Check descriptor engine status registers. This field should be set to 0 when the queue context is initialized.

[57] 1 irq_no_last

No interrupt was sent and the producer index (PIDX) or consumer index (CIDX) was idle in internal mode. When the irq_arm bit is set, the interrupt will be sent. This bit will clear automatically when the interrupt is sent or if the PIDX of the queue is updated.

This bit should be initialized to 0 when the queue context is initialized.

Not applicable for C2H ST.

[56:54] 3 port_id


The port id that will be sent on user interfaces for events associated with this queue.

[53] 1 irq_en

Interrupt enable.

An interrupt to the host will be sent on host status updates.

Set to 0 for C2H ST.

[52] 1 wbk_en

Writeback enable.

A memory write to the status descriptor will be sent on host status updates.

[51] 1 mm_chn For AXI-MM transfer, set to 0 to target Channel 0 or set to 1 to target Channel 1. For AXI-ST set to 0.
[50] 1 bypass

If set, the queue will operate under Bypass mode, otherwise it will be in Internal mode.

[49:48] 2 dsc_sz

Descriptor fetch size. 0: 8B, 1: 16B; 2: 32B; 3: 64B.

If bypass mode is not enabled, 32B is required for Memory Mapped DMA, 16B is required for H2C Stream DMA, and 8B is required for C2H Stream DMA.

If the queue is configured for bypass mode, any descriptor size can be selected. The descriptors will be delivered on the bypass output interface. It is up to the user logic to process the descriptors before they are fed back into the descriptor bypass input.

[47:44] 4 rng_sz Descriptor ring size index. This index selects one of 16 register (offset 0x204:0x240) which has different ring sizes.
[43:41] 3 reserved Reserved
[40:37] 4 fetch_max Maximum number of descriptor fetches outstanding for this queue. The max outstanding is fetch_max + 1. Higher value can increase the single queue performance,
[36] 1 at Address type of base address.

0: untranslated

1: translated

This will be the address type (AT) used on PCIe for descriptor fetches and status descriptor writebacks.

[35] 1 wbi_intvl_en

Write back/Interrupt interval.

Enables periodic status updates based on the number of descriptors processed.

Applicable to Internal mode.

Not Applicable to C2H ST. The writeback interval is determined by register QDMA_GLBL_DSC_CFG (0x250) bits[2:0].

[34] 1 wbi_chk

Writeback/Interrupt after pending check.

Enable status updates when the queue has completed all available descriptors.

Applicable to Internal mode.

[33] 1 fcrd_en

Enable fetch credit.

The number of descriptors fetched will be qualified by the number of credits given to this queue.

Set to 1 for C2H ST.

[32] 1 qen

Indicates that the queue is enabled.

[31:25] 7 reserved Reserved
[24:17] 8 fnc_id Function ID
[16] 1 irq_arm Interrupt arm. When this bit is set, the queue is allowed to generate an interrupt.
[15:0] 16 pidx Producer index.