QDMA Descriptor Bypass Output Ports - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-11-22
Version
3.4 English
Table 1. QDMA H2C Descriptor Bypass Output Port Descriptions
Port Name I/O Description
dma<n>_h2c_byp_out_dsc [255:0] O The H2C descriptor fetched from the host.

For H2C AXI-MM, the functional mode uses all 256 bits, and the structure of the bits are the same as this table.

For H2C AXI-ST, the functional mode uses [127:0] bits, and the structure of the bits are the same as this table.

dma<n>_h2c_byp_out_st_mm O Indicates whether this is a streaming data descriptor or memory-mapped descriptor.

0: streaming

1: memory-mapped

dma<n>_h2c_byp_out_dsc_sz [1:0] O Descriptor size. This field indicates the size of the descriptor.

0: 8B

1: 16B

2: 32B

3: 64B - 64B descriptors will be transferred with two valid/ready cycles. The first cycle has the least significant 32 bytes. The second cycle has the most significant 32 bytes. CIDX and other queue information is valid only on the second beat of a 64B descriptor .

dma<n>_h2c_byp_out_qid [1:0] O The QID associated with the H2C descriptor ring.
dma<n>_h2c_byp_out_error O Indicates that an error was encountered in descriptor fetch or execution of a previous descriptor.
dma<n>_h2c_byp_out_func [11:0] O PCIe function ID
dma<n>_h2c_byp_out_cidx [15:0] O

H2C Bypass Out Consumer Index

The ring index of the descriptor fetched. The User must echo this field back to QDMA when submitting the descriptor on the bypass-in interface.

dma<n>_h2c_byp_out_port_id [2:0] O QDMA port ID
dma<n>_h2c_byp_out_fmt[2:0] O Format

Tthe encoding for this field is as follows.

0x0: Standard descriptor

0x1 - 0x7: Reserved

dma<n>_h2c_byp_out_mm_chn O Channel number. Based on context settings it could be 0 or 1.
dma<n>_h2c_byp_out_valid O Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_h2c_byp_out_ready I Ready. When this interface is not used, Ready must be tied-off to 1.

The following is an example timing diagram for H2C Bypass Output:

Figure 1. H2C Bypass Output

Table 2. QDMA C2H Descriptor Bypass Output Port Descriptions
Port Name I/O Description
dma<n>_c2h_byp_out_dsc [255:0] O The C2H descriptor fetched from the host.

For C2H AXI-MM, the functional mode uses all 256 bits, and the structure of the bits is the same as this table.

For C2H AXI-ST, the functional mode uses [63:0] bits, and the structure of the bits is the same as this table. The remaining bits are ignored.

dma<n>_c2h_byp_out_st_mm O Indicates whether this is a streaming data descriptor or memory-mapped descriptor.

0: streaming

1: memory-mapped

dma<n>_c2h_byp_out_dsc_sz [1:0] O Descriptor size. This field indicates the size of the descriptor.

0: 8B

1: 16B

2: 32B

3:64B - 64B descriptors will be transferred with two valid/ready cycles. The first cycle has the least significant 32 bytes. The second cycle has the most significant 32 bytes. CIDX and other queue information is valid only on the second beat of a 64B descriptor.

dma<n>_c2h_byp_out_qid [1:0] O The QID associated with the H2C descriptor ring.
dma<n>_c2h_byp_out_error O Indicates that an error was encountered in descriptor fetch or execution of a previous descriptor.
dma<n>_c2h_byp_out_func [11:0] O PCIe function ID.
dma<n>_c2h_byp_out_cidx [15:0] O

C2H Bypass Out Consumer Index

The ring index of the descriptor fetched. The User must echo this field back to QDMA when submitting the descriptor on the bypass-in interface.

dma<n>_c2h_byp_out_port_id [2:0] O QDMA port ID
dma<n>_c2h_byp_out_pfch_tag[6:0] O Prefetch tag. The prefetch tag points to the cam that stores the active queues in prefetch engine
dma<n>_c2h_byp_out_fmt[2:0] O Format

The encoding for this field is as follows.

0x0 : Standard descriptor

0x1 - 0x7 : Reserved

dma<n>_c2h_byp_out_mm_chn O Channel number. Based on context settings it could be 0 or 1.
dma<n>_c2h_byp_out_valid O Valid. High indicates descriptor is valid, one pulse for one descriptor.
dma<n>_c2h_byp_out_ready I Ready. When this interface is not used, Ready must be tied-off to 1.

The following is an example timing diagram for C2H bypass Output:

Figure 2. C2H Bypass Output

It is common for dma<n>_h2c_byp_out_vld or dma<n>_c2h_byp_out_vld to be asserted with the CIDX value; this occurs when the Descriptor bypass mode option is not set in the context programming selection. You must set the Descriptor bypass mode during QDMA IP core customization in the AMD Vivado™ IDE to see descriptor bypass output ports. When Descriptor bypass option is selected in the AMD Vivado™ IDE but the descriptor bypass bit is not set in context programming, you see valid signals getting asserted with CIDX updates.