Allowed placements are shown in the table below. Placements are determined by CIPS IP configuration GUI as part of CPM configuration selections.
| Board | CPM5 PCIE Controller Width Configuration | GTYP Transceiver Quad (Package Bank) Channels | CPM5 PCIE Controller GTYP Reference Clock | Other Supported Width Configurations | Lane Reversal | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 0 | Quad 3 (Bank 105) | Quad 2 (Bank 104) | Quad 1 (Bank 103) | Quad 0 (Bank 102) | |||||||||||||||||
| 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 | 1 | 0 | |||||
| x16 | -- | x16 | Controller 0 [15:0] | -- | Quad 104, Refclk 0 | -- | By IP | |||||||||||||||
| x8, x8 | x8 | x8 | Controller 1 [7:0] | Controller 0 [7:0] | Quad 105, Refclk 0 | Quad 103, Refclk 0 | -- | By IP | ||||||||||||||
| x8 | x8 | -- | Controller 1 [7:0] | -- | Quad 105, Refclk 0 | -- | -- | By IP | ||||||||||||||
| x8 | -- | x8 | -- | Controller 0 [7:0] | -- | Quad 103, Refclk 0 | -- | By IP | ||||||||||||||
| x4, x4 | x4 | x4 | -- | Controller 1 [3:0] | -- | Controller 0 [3:0] | Quad 104, Refclk 0 | Quad 102, Refclk 0 | -- | On PCB | ||||||||||||
| x4 | x4 | -- | -- | Controller 1 [3:0] | -- | Quad 104, Refclk 0 | -- | -- | On PCB | |||||||||||||
| x4 | -- | x4 | -- | -- | Controller 0 [3:0] | -- | Quad 102, Refclk 0 | -- | On PCB | |||||||||||||
| x4, x8 | x4 | x8 | -- | Controller 1 [3:0] | Controller 0 [7:0] | Quad 104, Refclk 0 | Quad 103, Refclk 0 | -- | x4 on PCB x8 by IP |
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| x8, x4 | x8 | x4 | Controller 1 [7:0] | -- | Controller 0 [3:0] | Quad 105, Refclk 0 | Quad 102, Refclk 0 | -- | x8 by IP x4 on PCB |
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Board designs for x2 and x1 must use x4 guidance. For x2 board designs, based on the controller to be used, connect to controller lane numbers Controller 0 [1:0] or Controller 1 [1:0]. Similarly, for x1 board designs, connect to controller lane numbers Controller 0 [0] or Controller 1 [0].
Note: Controller lane numbers might not be the same as physical
GTYP channel numbers in a quad. Refer the provided placement table.