QDMA Management Ports - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2024-05-30
Version
3.4 English
Table 1. QDMA Management Ports
Port Name I/O Description
dma0_mgmt_req_adr[31:0] I QDMA register address
dma0_mgmt_req_dat[31:0] I data value to be written.
dma0_mgmt_req_cmd[1:0] I 2'b00 : read

2'b01 : write

2'b10 : reserved

2'b11 : reserved
dma0_mgmt_req_fnc[12:0] I Function number
dma0_mgmt_req_msc[5:0] I Reserved. Assign all zeroes
dma0_mgmt_req_rdy O Ready
dma0_mgmt_req_vld I Valid, asserted for one clock cycle if rdy is asserted
dma0_mgmt_cpl_dat[31:0] O Data from QDMA IP
dma0_mgmt_cpl_rdy I Ready
dma0_mgmt_cpl_sts[1:0] O
  • bit[0] :
    • 1 Error
    • 0 good
  • bit[1] :
    • 1 write response
    • 0 read response
dma0_mgmt_cpl_vld O Valid asserted for one clock cycle, if rdy is asserted

QDMA Management port should be connected to mailbox ports as described in CPM5 Mailbox IP.