XPIO Features

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

The XPIO are grouped into 54-pin banks with supporting resources for both high-performance and low-speed interfaces. Each XPIO can use the XPHY to align, serialize, and de-serialize a data stream. Each XPIO has I/O interconnect logic (IOL) resources to support low-speed SDR and DDR interfaces and coarse data alignment resources. The XPIO input and output buffers support a wide range of single-ended and differential I/O standards along with resources to support a high level of signal quality.

  • 1.0V, 1.2V, 1.35V, and 1.5V bank voltage standards
  • XPHY logic resources to align and serialize/de-serialize high-speed data streams
  • IOL logic resources to provide simplified lower-bandwidth SDR and DDR logic support
  • Internally generated VREF support shared across nibble boundaries
  • Calibrated output drive support
  • Calibrated internal termination
  • Internal differential termination
  • Internal bias support
  • Transmitter pre-emphasis and receiver equalization
  • Native support for MIPI D-PHY and ONFI interfaces
  • Supports serialization/deserialization ratios of 1:8, 1:4, and 1:2