When XPIO banking resources are located adjacent to certain resources such as
the processing system (PS) or high-speed transceiver columns, the XPIO bank will
have limited functionality. While clocking pins (GC) in corner banks will have full
access to clocking resources, non-clocking pins will be restricted to the memory
controller (referred to as DDRMC_ONLY) functionality. Because these restricted XPIO
bank are typically located at the corners of a device, they are referred to as
corner banks. Though usually defined along bank boundaries, in some instances a
partial bank on nibble boundaries might be restricted to DDRMC_ONLY use. Corner bank
locations vary by device and are explicitly called out in
Versal
Adaptive SoC Packaging and Pinouts Architecture Manual
(AM013) with a DDRMC Only designation. In pin planning a Versal device design, it is important to realize that
corner banks should only be used for DDRMC interfaces. When using the Advanced I/O
Planner for Advanced I/O Wizard designs, the corner banks are blocked from use.