Reset Sequence

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2024-03-18
Revision
1.5 English

An XPHY nibble can be reset through the process below. For interfaces that span multiple nibbles, apply the same sequence to all nibbles. Note that NIBBLESLICE[0] must be used for proper output delay calibration of each NIBBLESLICE in a nibble. If NIBBESLICE[0] is not used (implying that TX_RST[0] and RX_RST[0] would normally be tied to 1) but output delays are used in other NIBBESLICEs in the nibble, tie both TX_RST[0] and RX_RST[0] (not just TX_RST[0]) to 0 instead of 1.

The reset sequence for XPHY nibbles with SERIAL_MODE = FALSE (this is associated with source-synchronous designs) is shown below. Unless otherwise marked, all signals refer to the XPHY:

Note: Consider the following conditions before starting the reset sequence below:
  • Always keep PHY_WREN and PHY_RDEN deasserted during the reset sequence.
  • Always keep TX_EN_VTC and RX_EN_VTC asserted during the reset sequence.
  • RST, TX_RST, and RX_RST start as asserted.
  • XPLL.CLKOUTPHYEN starts as deasserted, and should be deasserted whenever RST is asserted or upon device power-on.
  • EN_VTC starts as deasserted. If external calibration is not required and VTC is being used, EN_VTC can be tied off to 1.
  1. Wait for XPLL.LOCKED_FB to assert. If multiple XPLLs are used to clock the interface, AND together each XPLL.LOCKED_FB of the XPLLs used to clock the interface.
  2. After the result of step 1 asserts, deassert RST, TX_RST, and RX_RST on all nibbles that compose the interface.
  3. Wait 64 CTRL_CLK cycles after the XPLL.LOCKED_FB AND gate asserts, then assert XPLL.CLKOUTPHYEN on all XPLLs used to clock the interface.
  4. AND the DLY_RDY from each nibble in the interface, and synchronize the result in your application's clock domain.
  5. After the AND of all DLY_RDYs in the interface from step (4) is 1, assert EN_VTC on all nibbles that compose the interface. If VTC is not used or REFCLK_FREQUENCY < 500MHz (for which EN_VTC should be tied to 0, and VTC and DELAY_VALUE _x are not supported), instead of asserting EN_VTC, skip to step 7 after the AND of all DLY_RDYs in the interface from step 4 is 1.
  6. AND the PHY_RDY from each nibble in the interface and wait for the output of this AND gate to be 1.
  7. Wait 16 CTRL_CLK cycles.
  8. After the 16th cycle, the reset sequence is considered complete if XPLL.LOCKED of all XPLLs that comprise the interface is 1. If XPLL.LOCKED_FB deasserts at any time, place all nibbles and XPLLs that compose the interface back into a reset state, defined by the bullet points prior to this sequence.
Figure 1. Source-Synchronous Reset Sequence

The reset sequence for XPHY nibbles with SERIAL_MODE = TRUE (any design that is not source-synchronous) is as follows. Unless otherwise marked, all signals refer to the XPHY:

Note: Consider the following conditions before starting the reset sequence below:
  • Always keep PHY_WREN and PHY_RDEN deasserted during the reset sequence.
  • Always keep TX_EN_VTC and RX_EN_VTC asserted during the reset sequence.
  • RST, TX_RST, and RX_RST start as asserted.
  • XPLL.CLKOUTPHYEN starts as deasserted, and should be deasserted whenever RST is asserted or upon device power-on.
  • This sequence assumes VTC is not used. Thus, EN_VTC should be deasserted or tied off to 1'b0.
  1. Wait for XPLL.LOCKED_FB to assert. If multiple XPLLs are used to clock the interface, AND together each XPLL.LOCKED_FB of the XPLLs used to clock the interface.
  2. After the result of step (1) asserts, deassert RST, TX_RST, and RX_RST on all nibbles that comprise the interface.
  3. Wait 64 CTRL_CLK cycles after the XPLL.LOCKED_FB AND gate asserts, then assert XPLL.CLKOUTPHYEN on all XPLLs used to clock the interface.
  4. AND the DLY_RDY from each nibble in the interface, and synchronize the result in your application's clock domain.
  5. After the result of step (4) asserts, wait an additional 16 CTRL_CLK cycles. After the 16th cycle, the reset sequence is considered complete if XPLL.LOCKED of all XPLLs that comprise the interface is 1. If XPLL.LOCKED_FB deasserts at any time, place all nibbles and XPLLs that comprise the interface back into a reset state, defined by the bullet points prior to this sequence.
Figure 2. Serial Mode Reset Sequence
Tip: If multiple nibbles comprise an interface, the assertion time for DLY_RDY can vary for each nibble. Within simulation, the assertion time of DLY_RDY does not vary for each nibble in an interface, but can vary from interface to interface.