Adjusting Receiver VREF Levels

To set custom receiver V_REF levels, the XPIO_VREF primitive can be used to assign a specific voltage level using the FABRIC_VREF_TUNE port. An optional V_REF scan feature in XP I/O banks helps to fine tune the internal V_REF of input buffers to maximize the performance for a subset of I/O standards. These features can be accessed through the IBUFE3 and IOBUFE3 primitives in conjunction with the XPIO_VREF primitive as shown in the following figure. V_REF scan requires building control logic into your interconnect logic design that will adjust and monitor the input to find an optimal V_REF threshold.

Figure 1. Access to the V_REF Scan

Internal V_REF tuning using the XPIO_VREF primitive controls the V_REF of six consecutive I/Os (one nibble group) within a bank as shown in the following figure. Inputs with I/O standards of different V_REF specifications cannot be placed within the same bank. A tuned V_REF connection (V_REF output of the XPIO_VREF primitive) cannot traverse nibble boundaries.

The 10-bit FABRIC_VREF_TUNE value provides scaling factors as a percentage of V_CCO as follows:

FABRIC_VREF_TUNE[9:0] = % VCCO * 1024 for LVSTL_11 and LVSTL06_12

For example, LVSTL06_12 uses the first equation and has a nominal V_REF level of 150 mV (or 12.5% of V_CCO). Because LVSTL06_12 is powered with a V_CCO of 1.2V, a FABRIC_VREF_TUNE value of 0010000000 or 128 can be used, as 128 (or 0010000000 = 0.125 * 1024 = 12.5% * 1.2V = 150 mV.

FABRIC_VREF_TUNE[9:0] = % VCCO * 512 for all other IOSTANDARDS

For example, SSTL12 has a target V_REF level of approximately 600 mV (50% V_CCO). A FABRIC_VREF_TUNE value of 0100000000 or 256 = 0.5 * 512 = 50% * 1.2V = 600 mV.

Important: Input signals for all standards other than LVSTL_11 and LVSTL06_12 are scaled by 50% compared to V_REF. The V_REF scan value must be chosen to account for the scaled value. For example, because SSTL12's target V_REF is 50% V_CCO, the V_REF scan value should be 0100000000₂, or 25% V_CCO, because the input signal is scaled before reaching the receiver. The Vivado tools always report V_REF levels relative to the input pin level (unscaled).

Figure 2. V_REF Scan Connection per Nibble within a Bank

Instantiating the XPIO_VREF Primitive

When instantiating the XPIO_VREF primitive, the following parameter must be set in the Vivado tools prior to implementation:

set_param place.disableMultipleVREFCheck true

In addition, the following constraint must be set in the XDC file to ensure the XPIO_VREF is placed and in the correct location. In the following example, a LOC on the XPIO_VREF instance must be LOCed to an appropriate site relative to the nibble that VREF is controlling (a and b in the following example are replaced with digital location designators adjacent to the nibble being controlled):

set_property LOC XPIO_VREF_XaYb [get_cells XPIO_VREF_inst]

Table 1. XPIO_VREF Primitive Attributes
Attribute	Description
ISTANDARD	The IOSTANDARD used in the NIBBLE when VREF_NIB is set to VREF_MC.
VREF_NIB	Describes the source of the VREF level control. Valid options are VREF_NIB, VREF_RIU, or VREF MC. When instantiating the XPIO_VREF attribute for fabric control of the level, VREF_FABRIC must be used. VREF_MC can be used when the nibble is using the default VREF level as defined by the standard in ISTANDARD. VREF_RIU is used when the XPHY is used and accessible through RIU address 0x41.

Table 2. XPIO_VREF Ports
Port	Description
FABRIC_VREF_TUNE<9:0>	Defines the VREF target level.
VREF	Port to connect to the IBUFE3 or IOBUFE3 primitive's VREF port.