Use Cases

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

In the IOL, IOB delays can be helpful in adjusting the clock to data timing relationship in an I/O interface. The IDELAYE5 and ODELAYE5 both must have delay levels registered at run time. Both the IDELAYE5 and ODELAYE5 use the same control ports to define the delay of the block. The CNTVALUEIN and LOAD ports are used to a specific delay value from 0 to 32 is known for the phase shift. The INC port can be used to incrementally increase or decrease the delay value from 0 to 32 taps. This is convenient when using a system that is intended to be calibrated during run time. Both methods for changing the delay value of the delay block are described in the following timing diagrams.

Note: The IDELAYE5 and ODLEAYE5 will always come out of configuration with a delay value of 0 taps. The delay value must be updated by user logic via either the VARIABLE or LOAD mode.
Figure 1. IDELAYE5 Delay