XP IOB Supported Single-Ended Standards

LVCMOS and LVDCI

The low-voltage CMOS standards (LVCMOS) is a widely used standard implemented with CMOS transistors. The LVDCI standard is a LVCMOS receiver with calibrated output impedance while the LVCMOS output impedance is defined by the DRIVE setting. LVCMOS12 (1.2V), LVCMOS15 (1.5V), and LVDCI_15 (1.5V) are supported in the XP IOB.

LVSTL and HSUL

The low-voltage swing terminated logic (LVSTL_11 and LVSTL06_12) and high-speed unterminated logic (HSUL_12) standards are optimized for lower-power memory interfaces. LVSTL06_12 is compatible with LVSTL06 interfaces but is powered at 1.2V.

HSTL and HSLVDCI

HSTL_I (1.5V) and HSTL_I_12 (1.2V) are both high-speed transceiver logic (HSTL) standards used for the general-purpose high-speed bus. Typically used for high-speed memory interfaces, these standards share the same receiver with the HSLVDCI_15 (1.5V) standard. The HSLVDCI_15 standard leverages a calibrated controlled impedance driver to allow operation without a split termination at the receiver, which are required by the HSTL standards.

POD

Pseudo open drain (POD) standards POD12 (1.2V) and POD10 (1.0V) are intended for DDR4 applications.

SSTL

The stub-series terminated logic (SSTL) I/O standards for 1.5V (SSTL15) and 1.35V (SSTL135) are used for general-purpose memory buses. SSTL15 is used for DDR3 SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3E. SSTL135 is used for DDR3L SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3-1. In XPIO banks, the SSTL15 IOSTANDARD can be used with a VOH attribute of 80 to drive 1.8V SSTL style receivers while still being powered by a 1.5V bank voltage. By using external termination and modifying the VREF level (see the XP IOB Internal VREF section) the receiver can accommodate 1.8V SSTL receive thresholds (0.9V). When interfacing with a 1.8V SSTL, care must be taken to ensure the external signal does not violate Versal adaptive SoC data sheet receiver specifications for a 1.5V powered bank.

UNDEFINED Default IOSTANDARD

When an IOSTANDARD is not defined by the user, the default assignment for the IOSTANDARD defaults to UNDEFINED. For a Versal device design to complete implementation, a non-default IOSTANDARD must be defined with one of the valid I/O standards described in this section. The UNDEFINED standard acts as a placeholder to allow a design to complete the early stages of implementation.