Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
Release Date
1.5 English
  • Banks located on the top and/or bottom periphery of the device
  • Banks are groups of 54 IOBs. Each IOB is capable of both single-ended and differential signaling.
  • VREF is internally generated (only)
  • DCI reference resistors are no longer required on a per bank basis (a maximum of two resistors per device)
  • Output drive and termination are calibrated against the DCI reference resistor
  • No support for 1.8V bank voltages. The supported bank voltages are 1.0V, 1.2V 1.35V, and 1.5V
  • Output drive strength support of 4 mA, 8 mA, and 12 mA
  • LVDS supported in 1.5V banks