SelectIO Resources Architecture

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

All AMD Versalâ„¢ devices have configurable SelectIO interface drivers and receivers, supporting a wide variety of standard interfaces. The robust feature set includes programmable control of output strength and slew rate, on-chip termination, and can internally generate a reference voltage (INTERNAL_VREF). Some Versal devices contain XPIO banks that contain 54 SelectIO pins and can implement both single-ended and differential I/O standards. XPIO banks support the high speed interfaces powered between 1.1V and 1.5V. Some Versal devices contain HDIO banks that can interface with voltage levels between 1.8V and 3.3V. The HDIO banks contain 22 SelectIO pins that can implement both single-ended I/O standards and differential I/O standards. Every SelectIO IOB resource contains input, output, and tristate drivers. The SelectIO pins can be configured to various I/O standards, both single-ended and differential.

  • Single-ended I/O standards are, for example, LVCMOS, LVTTL, HSTL, SSTL, HSUL, LVSTL, and POD
  • Pseudo-differential standards are, for example, differential HSTL, POD, HSUL, LVSTL, and SSTL
  • LVDS is the true differential standard.