FIFO - AM010

The CMPHY_OCTAD supports FIFOs for both the TX and RX datapaths.   The TX datapath FIFO allows fabric logic to transmit data to the CMPHY_OCTAD using a single clock domain. The X5IO PHY has been designed to minimize the latency through the transmitter’s FIFO.

The following figure shows a logical waveform for 16-bit data from the fabric being transmitted to the output pad DIFF_P. Fabric data PHY_DQ[15:0] is sent to the CMPHY_OCTAD as 16-bit data. The CMPHY_OCTAD then sends two 8-bit bytes of data to the X5PHIO_XCVR_X2.

Figure 1. 16-Bit TX with FIFO Serialization from Fabric

PHY_WREN is extended to eight bits to control whether the upper byte or lower byte of data is being transmitted. In the first clock cycle PHY_WREN transmits the upper byte PHY_D[15:8]. The tristate (X5IO PHY control) immediately reflects the PHY_WREN[7:0] settings from a logical perspective. Similarly, phy2xcv_wr_dq[7:0] also immediately reflects PHY_D0[15:8] and PHY_D0[7:0] based on PHY_CLK.

Within the X5PHIO_XCVR_X2, the write data is loaded up to 8 UIs with DIFF_P starting the transmission 1.4 ns later.

The following figure shows an 8-bit interface in which 4 bits of PHY_WREN[3:0] are used. In this case the CMPHY_OCTAD 8-bit data is sent to the X5PHIO_XCVR_X2 in parallel.

Figure 2. 8-Bit TX with FIFO Serialization from Fabric

The RX datapath FIFO can operate in three modes:

• FIFO_MODE_x = SYNC: Both read and write sides of the FIFO in BIT[x] share the same clock.
• FIFO_MODE_x = BYPASS: Forwards the data and FIFO write clock in BIT[x] to the programmable logic.
• FIFO_MODE_x = ASYNC: The read and write clocks of the FIFO in BIT[x] share the same frequency, but can be phase independent.

The following figure is representative of the FIFO operation for SYNC and ASYNC.

Figure 3. FIFO in RX Datapath (SYNC, ASYNC)

For BYPASS, as shown in the following figure, FIFO_EMPTY is always High and FIFO_RD_CLK is not used. For timing purposes the FIFO_RD_CLK must be left unconnected or connected to a static value to avoid the invalid timing of FIFO_RD_CLK which can alter a design's performance. In Bypass mode, the internally generated FIFO_WR_CLK is timed when clock constraints are applied to the DQS/Strobe pin by the X5IO Wizard.

Figure 4. FIFO in RX Datapath BYPASS

FIFO modes are controlled on a per-bit basis, as determined by the RXFIFO_MODE_<0-7> attribute. FIFO_MODE SYNC and ASYNC cannot be mixed in the same Octad. When the write and read pointers equal each other, FIFO_EMPTY is asserted. This is the starting point for the following ASYNC latency waveforms. If the read pointer is locked at one location (for example, FIFO_RDEN is deasserted) but the write pointer is still incrementing, after ten FIFO_WR_CLK cycles the write pointer wraps around to the read pointer location. When this occurs, new data appears at the Q<0-5> pin and FIFO_EMPTY is asserted again.

The following table describes FIFO-related attributes in a simplified way. For a complete description, refer to Attributes.

When FIFO_MODE_x = ASYNC

• FIFO_EMPTY can take two to three cycles to change values. The two to three cycle latency ensures that the write pointer is always two to three locations ahead of the read pointer.
• FIFO_RD_CLK must be the same frequency as FIFO_WR_CLK, but is phase independent.
• FIFO_EMPTY and Qx are in the FIFO_RD_CLK domain. DATAIN and Q in the following figures refer to a single BIT. DATAIN[x] maps to one of the Qx outputs. The waveforms show BIT[2], but apply to any BIT.