Uncalibrated Input Delay Primitive

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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Figure 1. IDELAYE5 Primitive

Table 1. IDELAYE5 Attributes
Attribute Values Description
CASCADE FALSE, TRUE The CASCADE attribute is set to TRUE when the ODELAYE5 is used to cascade the IDELAYE5. This attribute enables an input delay greater than 1.8 ns.
Table 2. IDELAYE5 Ports
Port I/O Description
DATAOUT Output Delayed data from the IOB
CNTVALUEOUT<4:0> Output The CNTVALUEOUT pins are used for reporting the current tap value and reads out the amount of taps in the current delay.
CASC_OUT Output Cascade delay to ODELAYE5 in cascade. The CASC_OUT pin is used when cascading from an IDELAYE5 to an ODELAYE5. The CASC_OUT port of the IDELAYE5 is connected to the CASC_IN of the ODELAYE5 in cascade.
IDATAIN Input Data from input pin
CASC_RETURN Input Cascade delay returning from the ODELAYE5 DATAOUT port. This port is used when cascading the ODELAYE5 and IDELAYE5.
CNTVALUEIN<4:0> Input The CNTVALUEIN pins are used for dynamically switching the loadable tap value. The CNTVALUEIN is the number of taps required.
CE Input Clock enable used in conjunction with INC port to increment (INC=1) or decrement (INC=0) the delay line. Leaving CE enabled for multiple CLK cycles will allow consecutive changes in the delay value.
CLK Input Clock used to sample LOAD, CE, and INC
INC Input Increment and decrement are controlled by the enable signal (CE).
  • INC = 1 increments
  • INC = 0 decrements
LOAD Input Load counter value from the CNTVALUEIN bus when High
RST Input The reset pin (RST) is asynchronous with the CLK