DQS_BIAS, DC_BIAS, and AC Coupling

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English


DQS_BIAS behaves as a logic 0 holding mechanism for undriven pins in pseudo-differential buffers (for example: DIFF_HSTL or DIFF_SSTL) by weakly pulling the P-side of the buffer to GND and the N-side of the buffer to VCCO. This allows an IDLE link to maintain a fixed logic level when a driver and termination are disabled on the link. The left circuit in the following figure shows DQS_BIAS behavior on pseudo-differential links.

The allowed values for the DQS_BIAS attribute for applicable I/O standards are TRUE and FALSE (DEFAULT) and are enabled using the following syntax:

set_property DQS_BIAS TRUE|FALSE [get_ports port_name]


DC_BIAS provides an internal bias to both P and N pins used as an input in scenarios where an AC coupled differential signal needs to be re-biased such that the LVDS15 receiver specifications are met. The DC_BIAS feature creates a bias through an equivalent voltage divider network to the bank's VCCO. The DC_BIAS attribute can be added to the XDC:

set_property DC_BIAS DC_BIAS_0|DC_BIAS_1|DC_BIAS_2|DC_BIAS_3 [get_ports port_name]
The DC_BIAS_1 setting provides the equivalent to 192 Ω at 20% VCCO. In a 1.5V bank, the combination of DIFF_TERM_ADV and DC_BIAS_1 provide an appropriate termination and bias for an AC coupled LVDS link without the need for bias or termination components on the PCB. DC_BIAS_2 provides the equivalent of 48Ω to 20% VCCO, but is not recommended for use with AC coupling due to a higher current draw caused by the voltage divider used to generate the equivalent 48Ω voltage divider. DC_BIAS_3 provides a 50Ω to GND bias which has very limited practical use as a bias network. With a LVDS15 IOSTANDARD used in a 1.5V bank, the combination of DC_BIAS_1 and DIFF_TERM_ADV provide both a bias and termination appropriate for many differential signals that require AC coupling. Because DC_BIAS can corrupt a weaker driver, it should not be used when the IOB is configured as an output or bidirectional.
Table 1. DC_BIAS Levels Explained
DC_BIAS Attribute Description
DC_BIAS_0 No Bias
DC_BIAS_1 192Ω to 20% VCCO. Suitable for AC coupling applications needing a weaker bias. DIFF_TERM_ADV or equivalent external 100Ω termination should be used with DC_BIAS_1. DIFF_TERM_ADV is only available in a 1.5V VCCO.
DC_BIAS_2 48Ω to 20% VCCO. Provides a strong bias and termination. DC_BIAS_2 should not be used with DIFF_TERM_ADV.
DC_BIAS_3 50Ω to GND. Care must be taken to ensure that GND biased signal does not violate input lower levels outlined in the data sheet.
Figure 1. DQS_BIAS and DC_BIAS Diagram

AC Coupling Recommendations

When receiving data from an AC coupled driver (like a clock source), care must be taken to ensure the appropriate bias levels are selected so that the receiver's input threshold requirements are met. If the receiver uses LVDS15 and resides in a 1.5V powered bank, a DC_BIAS value of DC_BIAS_1 along with DIFF_TERM_ADV setting of TERM_100 ensure that both a DC bias level and termination are provided inside the IOB for an AC coupled input. In scenarios where a 1.5V bank voltage is not used and AC coupling is required, it is recommended that both an external bias and external termination are used:

  • Do not use the optional internal differential termination.
    • DIFF_TERM = FALSE (default)
  • The differential signals at the input pins must meet the VIN requirements in the Recommended Operating Conditions table of the specific Versal adaptive SoC data sheets.
  • The differential signals at the input pins must meet the VIDIFF (minimum) requirements in the corresponding LVDS15 specifications tables of the specific Versal adaptive SoC data sheets.
  • The differential signals at the input pins must meet the VIDIFF (minimum) requirements in the corresponding LVDS15 specifications tables of the specific Versal adaptive SoC data sheets.

One way to accomplish this criteria is to use an external circuit that both AC-couples and DC-biases the input signals. The following figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF provides the 100Ω differential receiver termination because the internal DIFF_TERM_ADV = TERM_NONE. VBIAS should be a 1.0V to 1.5V source (typically VCCO) with an asymmetric termination structure that results in a VBIAS between 200 mV and 300 mV. Resistors in the 1K–10 KΩ range are recommended. The following figure is an example of an AC coupling network appropriate for a differential clock coming into a 1.2V powered bank.

Important: On all AC coupled interfaces there is a required settling time for the DC bias to charge to appropriate levels.
Figure 2. AC-Coupled with DC-Biased Differential Clock Input Example

The typical values for the AC coupling capacitors CAC are in the range of 100 nF. All components should be placed physically close to the device inputs. See the specific Versal adaptive SoC data sheets for the range of the bias voltage to be used in association with the external RDIFF resistor and the CAC AC coupling capacitors that will provide the appropriate bias for inputs without using the resistor network. As noted in XP IOB Pre-emphasis and Equalization, an AC coupled link is required when using receiver equalization with an LVDS15 interface. If receiver equalization is NOT desired on an AC coupled link, the EQUALIZATION attribute must be set to EQ_LEVEL0.