Controlling FIFO Modes

FIFO modes are controlled on a per-NIBBLESLICE basis, as determined by the FIFO_MODE_<0-5> attribute.

When the write and read pointers equal each other, FIFO_EMPTY is asserted. This is the starting point for the following ASYNC latency waveforms. If the read pointer is locked at one location (for example, FIFO_RDEN is deasserted) but the write pointer is still incrementing, after eight FIFO_WR_CLK cycles the write pointer wraps around to the read pointer location. When this occurs, new data appears at the Q<0-5> pin and FIFO_EMPTY is asserted again.

Recommended: Do not rely on FIFO_EMPTY asserting every eight FIFO_WR_CLK cycles for bit and word alignment. The first deassertion of FIFO_EMPTY should be used for controlling FIFO_RDEN.

Important: Do not register FIFO_EMPTY as part of the FIFO_RDEN = !FIFO_EMPTY connection when receiving a strobe (as opposed to a capture clock), regardless of if the flop is located in the BLI or PL. See Figure 1.

The following table describes FIFO-related attributes in a simplified way. For a complete description, refer to Attributes.

Table 1. FIFO-Related Attributes
Attribute	Description
FIFO_MODE_<0-5>	Determines the clocking topology of the FIFOs within the RX datapath.
RX_DATA_WIDTH	Determines the deserialization for the RX datapath, which affects the DATAIN to Qx mapping.

Mapping of DATAIN to Qx is shown in the following table, where DATAIN[x] corresponds to NIBBLESLICE[x]. Refer to the latency waveforms below for the context of P0, N0, …, P3, N3.

Table 2. DATAIN[x] to Qx Mapping
Deserialization (RX_DATA_WIDTH)	DATAIN[x]
Deserialization (RX_DATA_WIDTH)	N3	P3	N2	P2	N1	P1	N0	P0
1:8	Qx[3]	Qx[7]	Qx[2]	Qx[6]	Qx[1]	Qx[5]	Qx[0]	Qx[4]
1:4	–	–	–	–	Qx[3]	Qx[7]	Qx[2]	Qx[6]
1:2	–	–	–	–	–	–	Qx[3]	Qx[7]

When FIFO_MODE_x = ASYNC:

FIFO_EMPTY can take two to three cycles to change values
The two to three cycle latency ensures that the write pointer is always two to three locations ahead of the read pointer during operation
FIFO_RD_CLK must be the same frequency as FIFO_WR_CLK, but is phase independent
FIFO_EMPTY and Qx are in the FIFO_RD_CLK domain

DATAIN and Q in the following figures refer to a single NIBBLESLICE. DATAIN[x] maps to one of the Q_x outputs. The waveforms show NIBBLESLICE[2], but applies to any NIBBLESLICE.

Note: In ASYNC mode the FIFO_WR_CLK is available when using the Advanced I/O Wizard. Clock constraints applied to any Strobe/RdClk pins are not propagated to the FIFO_WR_CLK pins. Create a clock constraint on clock buffers generated by the FIFO_WR_CLK.

Figure 1. 8-bit RX Datapath Latency when FIFO_MODE_x = ASYNC

Figure 2. 4-bit RX Datapath Latency when FIFO_MODE_x = ASYNC

Figure 3. 2-bit RX Datapath Latency when FIFO_MODE_x = ASYNC

When FIFO_MODE_x = SYNC:

FIFO_EMPTY takes one cycle to change values when used with the XPLL deskew circuit.
A continuous receive data clock is assumed to allow the deskew circuitry to lock correctly.
Deskew circuitry for the XPLL is required to align the clock outputs to the FIFO_WR_CLK for optimal performance.
FIFO_EMPTY and Qx are in the FIFO_RD_CLK domain.
FIFO_WR_CLK is driven by the capture clock.
If TXRX_LOOPBACK_0 = TRUE, apply the create_clock constraint to DATAIN[0]. See Controlling TX to RX Loopback for more information on loopback.

Figure 4. 8-bit RX Datapath Latency when FIFO_MODE_x = SYNC

Figure 5. 4-bit RX Datapath Latency when FIFO_MODE_x = SYNC

Figure 6. 2-bit RX Datapath Latency when FIFO_MODE_x = SYNC

Note: Calibrated capture clock is shown when RX_GATING = DISABLE. When using CONTINUOUS_DQS = TRUE and RX_GATING = ENABLE, two additional clocks are needed due to the 2-stage synchronizer.

To align FIFO_RD_CLK to FIFO_WR_CLK, the FIFO_WR_CLK can be routed to an XPLL and use the deskew circuitry, as shown in the following figure. As a result, the FIFO_RD_CLK has a fixed phase alignment to FIFO_WR_CLK.

Figure 7. FIFO_WR_CLK Deskew Circuit

Figure 8. 8-bit RX Datapath Latency when FIFO_MODE_x = BYPASS

Figure 9. 4-bit RX Datapath Latency when FIFO_MODE_x = BYPASS

Figure 10. 2-bit RX Datapath Latency when FIFO_MODE_x = BYPASS

When FIFO_MODE_x = BYPASS, the XPHY data is transmitted from the FIFO_WR_CLK domain. To help closing timing and ensuring a consistent clock routing, connect the FIFO_WR_CLK to a deskew circuitry to align a clock buffer, as shown in Figure 7.