HD IOL Features

Single Data Rate Flip-Flops

Each pin contains local single-data rate (SDR) flip-flop registers in the IOB for both data and tristate lines. Both output, input, and tristate SDR flip-flops use these blocks:

FDCE: Flip-flip with clock enable and asynchronous clear
FDPE: Flip-flop with clock enable and asynchronous preset
FDRE: Flip-flop with clock enable and synchronous reset
FDSE: Flip-flop with clock enable and synchronous set

Important: When tristate control is used (that is, IOBUF/OBUFT) both data and tristate control paths must be used in the same manner (that is both SDR and DDR, or not registered at all).

Double Data Rate Flip-Flops

Each pin contains local double-data rate (DDR) flip-flop registers in the IOL for both data and tristate lines. The DDR flip-flops in the input path use the IDDRE1 and the output and tristate paths use the ODDRE1. When both data and tristate registers are used, it is required that Both data and tristate registers must be used in the same manner (that is both SDR, DDR, or not registered at all).

Special Considerations for Registered OBUFT/IOBUF Paths

When using the VC1902, VM1802, and VM1402 devices in HDIO banks, special considerations exist when using registered outputs. In these devices, when an HDIO output buffer with tristate control (OBUFT/IOBUF) is powered at 3.3V or 2.5V and both the data and tristate control signals toggle close in time to one another, a tristate-data race condition can occur. When using registered outputs for data and tristate, care should be taken to ensure data and tristate do not toggle at the same time. The following figure is one recommended solution to avoid this race condition. For more details see, AMD Answer 76846.

Figure 1. Tristate Race Fix

Figure 2. Tristate Race Fix Timing Diagram

Uncalibrated IOB Delay

Each pin has two uncalibrated delay blocks: one for the input delay (IDELAYE5) and one for the output path (ODELAYE5). Each individual block provides a uncalibrated delay of up at least 1.8 ns for both data and tristate paths when all taps are enabled. When only the input portion of the IOB is used, the ODELAYE5 can be cascaded to the IDELAYE5 to provide the input path of at least 3.6 ns of delay when all taps are enabled. Both IDELAYE5 and ODELAYE5 have 32 taps that can be changed incremented or decremented using the INC and CE pins, or can be dynamically changed using the CNTVALUEIN and LOAD pins. When using IDELAYE5 or ODELAYE5 in a single IOLOGIC site, a shared clock source must be shared between IDELAYE5 and ODELAYE5.

Note: Timing analysis only includes uncalibrated IOB delay when the LOAD pin is tied High and the CNTVALUEIN port is defined by tie offs.

Important: When tristate control is used (that is, IOBUF/OBUFT) both data and tristate control paths must use the same register structure and must both share the same ODELAY attributes. For example, both tristate and data paths must have the same ODELAY value OR must both bypass the ODELAY block.

DPLL

Each HDIO bank has an all-digital phase locked loop (DPLL) incorporated into the bank with the ability to phase shift the clock signal for optimal signal timing. The DPLL is used to generate new clock frequencies and to eliminate skew between clock and data paths as they reach the IDDR and ODDR registers.

For the Versal VC1902, VC1802, and VM1802 devices, the following restrictions related to DPLL apply:

The minimum input clock frequency (FINMIN_DPLL) is 50 MHz instead of 10 MHz.
DPLL PD deskew function and ZHOLD mode are not supported in the listed devices. MMCMs and IDELAY have to be used instead.
DPLLs in HDIO banks are not supported in the listed devices.

For more information, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).