XP IOL Resources

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

Although each I/O pin in an XP bank has access to an XPHY for high-speed interfaces, not all interfaces require the performance and logic associated with the XPHY. For I/O interfaces at speeds below 500 Mb/s, the XP IOL provides register-based interface logic. The XP IOL supports both single and double data rate registering of output, input, and tristate control. The IOL provides coarse alignment through the IODELAY block or one of four clock managers.