LVDS
In HD
IOB, the low-voltage differential signals (LVDS) standard LVDS_25 (2.5V) is a receiver
only standard with no internal termination options.
LVPECL
In
HD IOB, the LVPECL (3.3V) standard is a receiver only standard with no internal
termination options.
SLVS_400
In HD IOB, the SLVS-400_25 can be used to receive JESD8-13
signals.
Table 1. Allowed Attributes for LVDS25, LVPECL, and SLVS_400 I/O
Primitives
| Attributes |
IBUFDS/IBUFDSE3 |
| Allowed Values |
Default |
| IOSTANDARD |
LVDS_25, LVPECL,
SLVS_400_25 |
DIFF_SSTL
The DIFF_SSTL18 standard is defined by the JEDEC standard JESD8-15 and
is used for DDR2 SDRAM interfaces.
DIFF_HSTL
The differential high-speed transceiver logic (HSTL) standard
DIFF_HSTL_I_18 (1.8V) is a general-purpose high-speed bus standard defined by the JEDEC
standard JESD8-6.
Table 2. Allowed Attributes for DIFF_SSTL18_I and DIFF_HSTL_I_18 I/O
Primitives
| Attributes |
IBUF/IBUFE3 |
OBUF/OBUFT |
IOBUF/IOBUFE3 |
| Allowed Values |
Default |
Allowed Value |
Default |
Allowed Values |
Default |
| IOSTANDARD |
DIFF_SSTL18_I,
DIFF_HSTL_I_18 |
DIFF_SSTL18_I, DIFF_HSTL_I_18 |
DIFF_SSTL18_I,
DIFF_HSTL_I_18 |
| SLEW |
N/A |
FAST, SLOW |
SLOW |
FAST, SLOW |
SLOW |
| ODT |
RTT_48, RTT_NONE |
RTT_NONE |
N/A |
RTT_48, RTT_NONE |
RTT_NONE |
DIFF_UNDEFINED Default
IOSTANDARD
When an IOSTANDARD is not defined by the user, the default
assignment for the IOSTANDARD defaults to DIFF_UNDEFINED. For a Versal device design to complete implementation, a
non-default IOSTANDARD must be defined with one of the valid I/O standards described in
this section. The DIFF_UNDEFINED standard acts as a placeholder to allow a design to
complete the early stages or implementation.