Uncalibrated IOB Delay

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

Each pin has two uncalibrated delay blocks: one for the input delay (IDELAYE5) and one for the output path (ODELAYE5). Each individual block provides an uncalibrated delay of at least 1.8 ns for both data and tristate paths when all taps are enabled. When only the input portion of the IOB is used, the ODELAYE5 can be cascaded to the IDELAYE5 to provide the input path delay of at least 3.6 ns of delay when all taps are enabled. When using IDELAYE5 or ODELAYE5 in a single IOLOGIC site, a shared clock source must be shared between IDELAYE5 and ODELAYE5. Both IDELAYE5 and ODELAYE5 have 32 taps that can be incremented or decremented using the INC and CE pins, or can be dynamically changed using the CNTVALUEIN and LOAD pins. Because IOL delay elements are not calibrated, precise delay values should not be expected. When using the ODELAY block with tristate control, the tristate path will automatically have the same delay as the data line.

For both ODELAYE5 and IDELAYE5, the delay must be dynamically registered into the block at runtime. The tap delays can not be preset with attributes for the IDELAYE5 or ODELAYE5.

Note: Timing analysis only includes uncalibrated IOB delay when the LOAD pin is tied High, a CLK is driven by a clock, and the CNTVALUEIN port is defined by tie offs.
Important: When tristate control is used (that is, IOBUF/OBUFT) both data and tristate control paths must use the same register structure and must both share the same ODELAY attributes. For example, tristate and data path must both have the same ODELAY value OR must both bypass the ODELAY block.