Each pin has two uncalibrated delay blocks: one for the input delay
(IDELAYE5) and one for the output path (ODELAYE5). Each individual block provides an
uncalibrated delay of at least 1.8 ns for both data and tristate paths when all taps
are enabled. When only the input portion of the IOB is used, the ODELAYE5 can be
cascaded to the IDELAYE5 to provide the input path delay of at least 3.6 ns of delay
when all taps are enabled. When using IDELAYE5 or ODELAYE5 in a single IOLOGIC site,
a shared clock source must be shared between IDELAYE5 and ODELAYE5. Both IDELAYE5
and ODELAYE5 have 32 taps that can be incremented or decremented using the INC and
CE pins, or can be dynamically changed using the CNTVALUEIN and LOAD pins. Because IOL
delay elements are not calibrated, precise delay values should not be expected. When
using the ODELAY block with tristate control, the tristate path will automatically
have the same delay as the data line.
For both ODELAYE5 and IDELAYE5, the delay must be dynamically registered into the block at runtime. The tap delays can not be preset with attributes for the IDELAYE5 or ODELAYE5.