LVTTL
The LVTTL standard is a general-purpose EIA/JESD standard for 3.3V
applications that uses a single-ended CMOS input buffer and a push-pull output
buffer.
LVCMOS
The
low-voltage CMOS (LVCMOS) standards LVCMOS33 (3.3V), LVCMOS25 (2.5V), and LVCMOS18
(1.8V) are implemented with CMOS transistors. These standards are defined in the JEDEC
standards JESD8-7A, JESD8-5A, and JESD 8C.01.
Table 1. Allowed Attributes for LVTTL, LVCMOS18, LVCMOS25, and
LVCMOS33 I/O Primitives
| Attributes |
IBUF/IBUFE3 |
OBUF/OBUFT/IOBUF/IOBUFE3 |
| Allowed Values |
Default |
Allowed Values |
Default |
| IOSTANDARD |
LVTTL, LVCMOS18,
LVCMOS25, LVCMOS33 |
LVTTL, LVCMOS18,
LVCMOS25, LVCMOS33 |
| DRIVE |
N/A |
4, 8, 12 |
12 |
| SLEW |
N/A |
FAST, SLOW |
SLOW |
SSTL
SSTL18_I is defined by the JEDEC standard JESD8-15, and is used for DDR2
SDRAM interfaces. For some topologies (such as short, point-to-point interfaces), the
class-I driver can result in reduced overshoot and better signal integrity.
HSTL
The
high-speed transceiver logic (HSTL) HSTL_I_18 (1.8V) standard is a general-purpose
high-speed bus standard as defined by the JEDEC standard JESD8-6.
Table 2. Allowed Attributes for SSTL18_I and HSTL_I_18 I/O
Primitives
| Attributes |
IBUF/IBUFE3 |
OBUF/OBUFT |
IOBUF/IOBUFE3 |
| Allowed Values |
Default |
Allowed Value |
Default |
Allowed Values |
Default |
| IOSTANDARD |
SSTL18_I,
HSTL_I_18 |
SSTL18_I,
HSTL_I_18 |
SSTL18_I,
HSTL_I_18 |
| SLEW |
N/A |
FAST, SLOW |
SLOW |
FAST, SLOW |
SLOW |
| ODT |
RTT_48, RTT_NONE |
RTT_NONE |
N/A |
RTT_48, RTT_NONE |
RTT_NONE |
UNDEFINED Default
IOSTANDARD
When an IOSTANDARD is not defined by the user, the default
assignment for the IOSTANDARD defaults to UNDEFINED. For a Versal device design to complete implementation, a non-default IOSTANDARD
must be defined with one of the valid I/O standards described in this section. The
UNDEFINED standard acts as a placeholder to allow a design to complete the early stages
or implementation.