XP IOB Banking Structure

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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The XPIO pins are grouped into banks of 54 IOBs (27 I/O pairs) with each IOB having associated XP IOL logic and shared XPHY logic. Within a bank, there are six pin groupings, defined as a nibble, which share XPHY logical resources, as shown in the following figure. Within a nibble, each pin has an associated pin pair that can used to accommodate differential signaling standards. All IOBs in an XP bank share the same VCCO power supply that is used to power driver logic, receiver logic, and termination. Regardless of whether the IOB is used as an input, output, or bidirectional pin, each I/O standard has a specific VCCO voltage requirement that must be used for the I/O standard to populate a bank. Similarly, each pin in a nibble must share a compatible INTERNAL_VREF level with all the other pins in a nibble.

Important: Some XPIO banks (typically located on the corner of the device) have pins that have limited function and can only be used for DDR memory controller functionality. See the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for specific pin information.
Figure 1. XP Bank (54 IOB, 27 I/O Pairs, 9 Nibbles, 54 XIOL)