The XPIO pins are grouped into banks of 54 IOBs (27 I/O pairs) with each IOB having associated XP IOL logic and shared XPHY logic. Within a bank, there are six pin groupings, defined as a nibble, which share XPHY logical resources, as shown in the following figure. Within a nibble, each pin has an associated pin pair that can used to accommodate differential signaling standards. All IOBs in an XP bank share the same VCCO power supply that is used to power driver logic, receiver logic, and termination. Regardless of whether the IOB is used as an input, output, or bidirectional pin, each I/O standard has a specific VCCO voltage requirement that must be used for the I/O standard to populate a bank. Similarly, each pin in a nibble must share a compatible INTERNAL_VREF level with all the other pins in a nibble.
Corner Banks and PL Only Pins
When XP banking resources are located adjacent to certain resources such as the processing system (PS) or high-speed transceiver columns, the XP bank might have limited functionality. While clocking pins (GC) in corner banks have full access to clocking resources, non-clocking pins are restricted to the memory controller (DDRMC) functionality. Because these restricted XP bank are typically located at the corners of a device, they are referred to as corner banks. Though usually defined along bank boundaries, in some instances a partial bank on nibble boundaries might be restricted to DDRMC use. Corner bank locations vary by device and are explicitly called out in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) with a DDRMC designation. In pin planning a Versal device design, it is important to realize that corner banks should only be used for DDRMC interfaces. When using the Advanced I/O Planner for Advanced I/O Wizard designs, the corner banks are blocked from use.
In addition to corner banks (which only have DDRMC functionality), there can be XP pins in a device that have PL access but no DDRMC access. A DDRMC can span three XP banks. In some devices, XP pins might exist but do not connect to a DDRMC, often referred to as "PL only" pins. These XP IOB banks have standard PL access but do not have connections to the DDRMC. It is important to refer to Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) when planning a layout to ensure a given bank has the necessary function needed.