All high-performance interfaces must be accessed using the Advanced I/O Wizard (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)). It constructs all connections (including inter-nibble and inter-byte clocking), handles the reset sequence, and optimizes the XPHY and I/O hardware. The wizard has setup options for synchronous and asynchronous interfaces, and multiple instances can be built with multiple instantiations of the wizard. The XPHY NIBBLESLICEs not used by the wizard are available to the XP IOL or for direct IOB feed-through to the programmable logic. A pin cannot be connected simultaneously to both an XPHY nibble and directly to fabric. In conjunction with the Advanced I/O Wizard, the Advanced I/O Planner simplifies XPHY pin planning with a GUI approach to place and constrain any XPHY based interface.
set_property DELAY_VALUE_XPHY <desired delay in ps> [get_ports <top-level port(s) that ultimately connect to DATAIN or O0>]implement_xphy_cores -update_delay_value_onlyBoundary logic interface (BLI) flip-flops can be used on certain XPHY signals to improve timing. See Boundary Logic Interface for more information.