XPHY Usage

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

All high-performance interfaces must be accessed using the Advanced I/O Wizard (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)). It constructs all connections (including inter-nibble and inter-byte clocking), handles the reset sequence, and optimizes the XPHY and I/O hardware. The wizard has setup options for synchronous and asynchronous interfaces, and multiple instances can be built with multiple instantiations of the wizard. The XPHY NIBBLESLICEs not used by the wizard are available to the XP IOL or for direct IOB feed-through to the programmable logic. A pin cannot be connected simultaneously to both an XPHY nibble and directly to fabric. In conjunction with the Advanced I/O Wizard, the Advanced I/O Planner simplifies XPHY pin planning with a GUI approach to place and constrain any XPHY based interface.

Important: LVCMOS is not compatible with XPHY.
To aid in setting input and output delays to a time-based value, the following Tcl commands can be used to set them through the top-level port connecting to DATAIN or O0 rather than setting the DELAY_VALUE_# attribute. Like the DELAY_VALUE_# attribute, setting DELAY_VALUE_XPHY on a NIBBLESLICE changes the value of both the input and output delay lines:
set_property DELAY_VALUE_XPHY <desired delay in ps> [get_ports <top-level port(s) that ultimately connect to DATAIN or O0>]
The command above prepares the delays to be applied, then the command below applies them. Thus, you can issue multiples of the command above before finalizing all of them through the following implement_xphy_cores command:
implement_xphy_cores -update_delay_value_only

Boundary logic interface (BLI) flip-flops can be used on certain XPHY signals to improve timing. See Boundary Logic Interface for more information.