Boundary Logic Interface

In addition to clocking resource, XPIO banks provide register stages for both signals going into and coming out of the programmable logic space to and from XPIO. Because this resource exists between both types of XPIO logic resources (XPHY and XPIOL) and programmable logic regions, these logical blocks are called the boundary logic interface (BLI). In certain configurations, these BLI register stages can help optimize the timing of an interface. To implement registers in the BLI region, an FDCE or FDRE primitive can be instantiated in a design leveraging the BLI attribute:

set_property BLI TRUE|FALSE [get_cells register_name]

BLI registers have a few restrictions that FDRE and FDCE typically do not have. BLI registers cannot be assigned an initial value, and BLI registers do not have synchronous reset capabilities. When leveraging BLI registers, it can be helpful to leverage directives like EXTRACT_RESET = "no" in the Vivado Design Suite.

Both single data rate and double data rate paths to and from the XP IOL can either use or bypass BLI registers. For the XPHY, several signals can leverage the BLI. See the following table for specific XPHY signals that can leverage BLI registers. In the table, DIV_CLK = REFCLK_FREQUENCY / TX_DATA_WIDTH.

Each BLI register has a fixed routing to a specific XPHY port. As a result, each bit within a bus must be connected to a separate BLI register.