XPHY Nibble

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

XPHY is the high-performance I/O interface for an XPIO bank. Every XPIO bank has nine XPHY nibbles. Each XPHY nibble is defined as six XPHY NIBBLESLICEs and its associated features. XPHY NIBBLESLICEs contain input and output logic, composed of a serializer, deserializer, I/O delays, and a receiver FIFO. XPHY NIBBLESLICEs can operate as a transmitter, receiver, or bidirectional circuit. An XPHY nibble also performs the following functions/features:

  • Built-in self-calibration (BISC) aids in alignment and uses voltage and temperature compensation (VTC) to adjust delay lines
  • Generates clocks for the receiver and transmitter functions in the XPHY NIBBLESLICEs
  • Gives access to the register interface unit (RIU) that provides access to all features of an XPHY nibble
  • Tristate control
  • TX to RX loopback
  • Serial mode, which supports receiver interfaces where the clock and data phase relationship is unknown (any interface that is not source-synchronous)

The layout of XPHY nibbles in an XPIO bank is represented in the following figure.

Figure 1. Relationship of XPHY Nibble, XP IOL, and IOB within an XPIO Bank

The following figure is a detailed view of the previous figure, representing the relationship between a single XPHY nibble, XP IOL, and IOB within an XPIO bank.

Figure 2. Relationship Between a Single XPHY Nibble, XP IOL, and IOB

The following figure shows an XPHY NIBBLESLICE.

Figure 3. XPHY NIBBLESLICE with TX and RX Datapaths