HDIO Features

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

The HDIOs are grouped into 22-pin banks with supporting resources for low-performance interfaces. Each HDIO has IOL resources to simplify the support for low-speed SDR and DDR interfaces and coarse data alignment resources. In addition to logic, the HDIO output buffers provide resources to drive single-ended and pseudo-differential standards. The HDIO input buffers can receive several single-ended and differential standards. HDIOs are optimized for single-ended, voltage-referenced, and pseudo-differential I/O standards operating at low data rates.

  • IOL logic resources support low-speed interfaces with SDR and DDR logic
  • IODELAY can provide at least 1.8 ns uncalibrated output delay
  • IODELAY can be cascaded with output delay to provide at least 3.6 ns uncalibrated input delay
  • 1.8V, 2.5V, and 3.3V bank voltage I/O standard support
  • Uncalibrated output drive and slew control
  • Internal VREF on a bank-wide resolution
  • LVDS and LVPECL input support with external termination