Double Data Rate Output Flip-Flop

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

Versal devices have registers in the IOL to implement output DDR registers as in previous generations. This feature is accessed when instantiating the ODDRE1 primitive. DDR multiplexing is automatic when using the ODDRE1. No manual control of the multiplexer select is needed. This control is generated from the clock. The ODDRE1 primitive supports only the SAME_EDGE mode of operation. The SAME_EDGE mode allows designers to present both data inputs to the ODDRE1 primitive on the rising edge of the ODDRE1 clock, which saves CLB and clock resources and increases performance.

Figure 1. ODDRE1 Primitive

Table 1. ODDRE1 Attributes
Attribute Values Description
SRVAL 1'b0, 1'b1 Initializes the value of the ODDRE1 flip-flops
Table 2. ODDRE1 Ports
Port I/O Description
Q Output ODDRE1 register output
C Input Clock input pin
D1,D2 Input ODDRE1 register inputs
SR Input Asynchronous High reset