XP XPHY Architecture

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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1.5 English

XPHY is the high-performance I/O interface on the AMD Versal™ adaptive SoC XPIOs. There are nine XPHY nibbles in an XPIO bank, with each XPHY nibble containing six XPHY NIBBLESLICEs that transmit and/or receive data from six individual I/O pins, for a total of 54 pins per bank. Each XPHY NIBBLESLICE is composed of a serializer, deserializer, I/O delays, and a receiver FIFO. The Versal device XPHY is equipped with voltage and temperature compensation (VTC) and a mechanism for automatic delay adjustment for optimal data eye centering through the built-in self-calibration (BISC) feature in each XPHY nibble. I/O delays can also be controlled through the programmable logic. Control of the XPHY features is available through the register interface unit (RIU) in each nibble.

XPHY is used to support the following applications:

  • DDR4 and LPDDR4 integrated memory controllers supported through the IP catalog in the AMD Vivado™ tools
  • QDR IV and RLDRAM3 memory controllers supported through the IP catalog in the Vivado tools
  • MIPI D-PHY v1.2
  • Gigabit Ethernet 1000Base-X and SGMII
  • High-speed source-synchronous and asynchronous I/O interfaces supported through the Advanced IO Wizard in the IP catalog of the Vivado tools
  • IOB feed-through to programmable logic