Calibrated Termination (Digitally Controlled Impedance)

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
Release Date
1.5 English

To provide the highest precision termination, external reference resistors must be provided to calibrate the internal device termination. Some banks will have an IO_VR pin that must have a 240Ω reference resistor pulled up to the VCCO powering the bank in which the IO_VR pin is located. The reference resistor is used to calibrate all I/O banks on the same half of the device. Banks containing an IO_VR pin must always be powered by a valid VCCO level.

Important: The IO_VR pins must have an external 240Ω resistor tied to the bank VCCO. These pins are dedicated and cannot be used as user I/O. All designs must populate these pins appropriately, regardless of the I/O standards used in a design.
Figure 1. IO_VR_700 Pin

In previous FPGA generations, specific IOSTANDARDs ending in _DCI were required to enable the internal calibration circuitry (DCI). In the Versal architecture, the reference calibration circuitry is always enabled and _DCI specific standards are not required to enable calibrated termination.

The XP IOB provides several types of calibrated termination:

  • Split-termination input impedance (termination to VCCO/2)
  • Single-termination input impedance (termination to VCCO or termination to GND)
  • Source termination

Each type of termination allows the selection of termination strengths to accommodate 40Ω, 48Ω, and 60Ω interfaces. Single-termination input impedance offsets a pull type to either VCCO or GND depending on the standard (see the XP IOB Supported Standards section for further information).

On-Die Termination Attribute

The on-die termination (ODT) attribute supports split or single termination on the inputs of the HSTL, SSTL, POD, LVSTL, and HSUL standards. The advantage of using ODT over discrete resistors is that signal integrity is improved by completely removing any PCB trace stubs at the receiver. The ODT attribute is used to define the value of the on-die termination at the input. The VCCO of the I/O bank must be connected to the appropriate voltage level for the ODT attribute to perform as expected. When ODT is used for differential buffers, both P and N pins have the same termination.

The ODT_SPLIT termination is for memory interfaces that use the SSTL or HSTL type I/O standards. SPLIT termination provides termination that centers the signal around the VREF input threshold level. As shown in the following diagram, in Versal devices this termination is implemented internally with 2R pulled up to VCCO and 2R pulled down to GND, creating a symmetric equivalent termination of R to VCCO/2.

Figure 2. ODT_SPLIT

ODT_SINGLE termination provides termination to VCCO or GND and is used in open-drain I/O standards (POD or LVSTL). The standard used defines whether the ODT is terminated to VCCO or GND (see the supported I/O standards table) and is implemented with a single R structure to VCCO or GND as shown in the following figure.

Figure 3. ODT_SINGLE

The ODT attribute uses the following syntax in the XDC file:
set_property ODT value [get_ports port_name]
Values can be RTT_40, RTT_48, and RTT_60 for termination values of 40Ω, 48Ω, or 60Ω, respectively. RTT_40 is the default ODT setting.

For source termination, Versal devices provide calibrated output impedance control.

Figure 4. Controlled Output Termination

Values can be RDRV_40, RDRV_48, and RDRV_60 for termination values of 40Ω, 48Ω, or 60Ω, respectively.

set_property OUTPUT_IMPEDANCE value [get_ports port_name]


Bidirectional primitives that use ODT (SPLIT or SINGLE) internal termination have a DCITERMDISABLE port that allows you to disable internal input termination. Asserting this port High can help save power during long periods of IDLE time on an interface.