Ports

The following table lists ports and their descriptions. For ports with width [5:0], each element maps to the NIBBLESLICE with the matching number. For example, DATAIN[0] is the incoming data to NIBBLESLICE[0], DATAIN[1] is the incoming data to NIBBLESLICE[1], and so on.

Some ports can be connected through the Boundary Logic Interface (BLI). For more information on which ports can be connected, see Boundary Logic Interface.

Note: All high-performance interfaces must be accessed using the Advanced I/O Wizard (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)).

Table 1. XPHY Ports
Port Name	Width	Input/Output	Clock Domain	Description
BISC_START_IN		Input	–	This is a simulation-only port required for BISC. If an interface is composed of multiple nibbles, connect this port to BISC_START_OUT of the next nibble in the daisy chain. If an interface is composed of only one nibble or this port is on the last nibble in the daisy chain, connect this port to BISC_STOP_OUT of the same nibble.
BISC_STOP_IN		Input	–	This is a simulation-only port required for BISC. If an interface is composed of multiple nibbles, connect this port to BISC_STOP_OUT from the previous nibble in the daisy chain. If an interface is composed of only one nibble or this port is on the first nibble in the daisy chain, tie this port High.
CE	[5:0]	Input	CTRL_CLK	Used with INC, LD, and CNTVALUEIN to change delay values on a per-NIBBLESLICE basis. When updating an input or output delay in NIBBLESLICE[x] through the RIU, CE must be set to 0. Refer to Controlling Delays for how to set CE, LD, INC, and CNTVALUEIN to get the desired delay change.
CLK_FROM_OTHER_XPHY		Input	–	Input for an inter-byte clock from certain nibbles. In being part of inter-byte clocking, CLK_FROM_OTHER_XPHY can only be connected to CLK_TO_LOWER or CLK_TO_UPPER of another nibble and cannot be connected to the programmable logic. CLK_FROM_OTHER_XPHY of the source nibble starting the inter-byte clocking should be set to 1'b1. The Clocking section lists the nibbles that are capable of inter-byte clocking with each other.
CNTVALUEIN	[53:0]	Input	CTRL_CLK	The delay value (in taps) to be loaded to the input or output delay selected by RXTX_SEL. Each NIBBLESLICE is associated with 9b of CNTVALUEIN. NIBBLESLICE[0] is associated with CNTVALUEIN[8:0], NIBBLESLICE[1] with CNTVALUEIN[17:9], NIBBLESLICE[2] with CNTVALUEIN[26:18], NIBBLESLICE[3] with CNTVALUEIN[35:27], NIBBLESLICE[4] with CNTVALUEIN[44:36], and NIBBLESLICE[5] with CNTVALUEIN[53:45]. Refer to Controlling Delays for how to set CE, LD, INC, and CNTVALUEIN to get the desired delay change.
CTRL_CLK		Input	–	Clock used for RIU access, delay line updates, and BISC. CTRL_CLK must be driven by a free-running clock. The ratio of different CTRL_CLK frequencies of all nibbles in a bank cannot be greater than 4:1.
DATAIN	[5:0]	Input	ASYNC	RX data from the IOB. DATAIN[0] enters NIBBLESLICE[0], DATAIN[1] enters NIBBLESLICE[1], and so on. The data is collected and stored in the FIFO of the corresponding NIBBLESLICE, after which it is output on the corresponding Q port (Q0 maps to NIBBLESLICE[0], etc.). The Controlling FIFO Modes section has more details on this mapping.
D0	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[0]. After being serialized, D0 is output on O0[0]. The Controlling Tristate Control section describes how D0 is serialized for different data widths.
D1	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[1]. After being serialized, D1 is output on O0[1]. The Controlling Tristate Control section describes how D1 is serialized for different data widths.
D2	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[2]. After being serialized, D2 is output on O0[2]. The Controlling Tristate Control section describes how D2 is serialized for different data widths.
D3	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[3]. After being serialized, D3 is output on O0[3]. The Controlling Tristate Control section describes how D3 is serialized for different data widths.
D4	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[4]. After being serialized, D4 is output on O0[4]. The Controlling Tristate Control section describes how D4 is serialized for different data widths.
D5	[7:0]	Input	PLL_CLK	TX data from the programmable logic for NIBBLESLICE[5]. After being serialized, D5 is output on O0[5]. The Controlling Tristate Control section describes how D5 is serialized for different data widths.
EN_VTC		Input	ASYNC	Assert to enable VTC for a nibble. If asserted without RX_EN_VTC/TX_EN_VTC, only QTR delays undergo VTC.
FIFO_RDEN		Input	FIFO_RD_CLK	When HIGH, increments the FIFO read pointer every FIFO_RD_CLK cycle to read data from the FIFO. Keep asserted every cycle that data is moved from the FIFO to the programmable logic.
FIFO_RD_CLK		Input	–	The FIFO read clock.
INC	[5:0]	Input	CTRL_CLK	Used with CE, LD, and CNTVALUEIN to change delay values on a per-NIBBLESLICE basis. When updating an input or output delay in NIBBLESLICE[x] through the RIU, INC is a don't care. Refer to Controlling Delays for how to set CE, LD, INC, and CNTVALUEIN to get the desired delay change.
LD	[5:0]	Input	CTRL_CLK	Used with CE, INC, and CNTVALUEIN to change delay values on a per-NIBBLESLICE basis. When updating an input or output delay in NIBBLESLICE[x] through the RIU, LD must be set to 1. Refer to Controlling Delays for how to set CE, LD, INC, and CNTVALUEIN to get the desired delay change.
NCLK_NIBBLE_IN		Input	–	N-clk input for an inter-nibble clock from certain nibbles. In being part of inter-nibble clocking, NCLK_NIBBLE_IN can only be connected to NCLK_NIBBLE_OUT of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-nibble clocking.
PCLK_NIBBLE_IN		Input	–	P-clk input for an inter-nibble clock from certain nibbles. In being part of inter-nibble clocking, PCLK_NIBBLE_IN can only be connected to PCLK_NIBBLE_OUT of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-nibble clocking.
PHY_RDCS0	[3:0]	Input	PLL_CLK	This port is only for memory-related use.
PHY_RDCS1	[3:0]	Input	PLL_CLK	This port is only for memory-related use.
PHY_RDEN	[3:0]	Input	See description	PHY_RDEN controls accepting or rejecting the strobe entering on NIBBLESLICE[0] or from inter-nibble clocking, depending upon the settings of CONTINUOUS_DQS, RX_GATING, and RX_DATA_WIDTH. Always ensure the strobe has stabilized and BISC has completed before asserting PHY_RDEN. Refer to Controlling Built-in Self-Calibration for when BISC is considered completed. PHY_RDEN control is outlined in the next section: PHY_RDEN must be deasserted during the reset sequence and when issuing a BS_RESET from the RIU interface. When RX_DATA_WIDTH = don't care, RX_GATING = ENABLE, and CONTINUOUS_DQS = TRUE, then the four bits of PHY_RDEN are OR'd together and that output is used to control the gate. If the result of the OR operation is `1`, then the capture clock is accepted. If it is `0`, then the capture clock is rejected. PHY_RDEN is synchronized to the capture clock for this attribute combination. Setting CONTINUOUS_DQS = TRUE requires that two capture clock cycles be received prior to receiving data to prevent data loss. When RX_DATA_WIDTH = 4 or 8, RX_GATING = ENABLE, and CONTINUOUS_DQS = FALSE, set the following bits of PHY_RDEN to `1` to accept the strobe or `0` to reject the strobe. PHY_RDEN is synchronized to PLL_CLK for this attribute combination. Each bit of PHY_RDEN controls two UI worth of data: If RX_DATA_WIDTH = 8: [3:0] If RX_DATA_WIDTH = 4: [2][0] If RX_DATA_WIDTH = 2: not supported When RX_GATING = DISABLE the gate is always open, regardless of the value of RX_DATA_WIDTH, CONTINUOUS_DQS, or PHY_RDEN. When SERIAL_MODE = TRUE, tie all four bits High. When the interface is only TX, tie PHY_RDEN to 0. See Bidirectional Datapath for more information.
PHY_WRCS0	[3:0]	Input	PLL_CLK	This port is only for memory-related use.
PHY_WRCS1	[3:0]	Input	PLL_CLK	This port is only for memory-related use.
PHY_WREN	[3:0]	Input	PLL_CLK	When TBYTE_CTL_x is set to PHY_WREN, the PHY_WREN input is inverted and serialized by the XPHY before being used as the tristate control signal (T_OUT[x]) for NIBBLESLICE[x]. The inverted and serialized PHY_WREN is output on T_OUT synchronously with the TX data. Unlike T, which has each of its bits mapped to a NIBBLESLICE, PHY_WREN is applied to each NIBBLESLICE in a nibble. Each bit of PHY_WREN controls the tristate enable of two UIs worth of data. PHY_WREN is not supported when TX_DATA_WIDTH = 2. See Controlling Tristate Control for more information. PHY_WREN must be deasserted during the reset sequence and when issuing a BS_RESET from the RIU interface. When TX_GATING = ENABLE, PHY_WREN gates the TX datapath of NIBBLESLICE[0], NIBBLESLICE[2], NIBBLESLICE[3], NIBBLESLICE[4], and NIBBLESLICE[5]. NIBBLESLICE[1] cannot be gated. Set the following bits of PHY_WREN to `0` to gate transmit data or `1` to not gate transmit data (PHY_WREN is serialized but not inverted when used for gating). If TX_DATA_WIDTH = 8: [3:0] If TX_DATA_WIDTH = 4: [2][0] If TX_DATA_WIDTH = 2: not supported See Bidirectional Datapath for more information.
PLL_CLK		Input	–	Clocks the XPHY interface (clocks within the interface are generated from this). Must be connected to CLKOUTPHY of an XPLL capable of routing to the nibble. If PLL_CLK is less than 500 MHz, DELAY_VALUE_<0-5> and VTC are not supported. Set the REFCLK_FREQUENCY attribute to the same value as the PLL_CLK frequency.
RIU_ADDR	[7:0]	Input	CTRL_CLK	Address bus to access RIU
RIU_NIBBLE_SEL		Input	CTRL_CLK	Assert to perform read/write operations on the RIU
RIU_WR_DATA	[15:0]	Input	CTRL_CLK	Write data for the RIU
RIU_WR_EN		Input	CTRL_CLK	Assert high to enable writes to the RIU. RIU writes also require that RIU_RD_VALID is HIGH. See Register Interface Unit for more information.
RST		Input	ASYNC	Resets the entire XPHY nibble, including all RX datapaths, TX datapaths, and delays. While RST is asserted, all TX IOBs and the tristate control signal are set to the values of TX_INIT_# and TX_INIT_TRI, respectively.
RXTX_SEL	[5:0]	Input	CTRL_CLK	When `0`, RXTX_SEL applies CE, INC, LD, and CNTVALUEIN to the input delay. Similarly, the input delay value is reported by CNTVALUEOUT. When `1`, RXTX_SEL applies CE, INC, LD, and CNTVALUEIN to the output delay. Similarly, the output delay value is reported by CNTVALUEOUT.
RX_EN_VTC	[5:0]	Input	ASYNC	Assert to enable the Alignment and Delay Calibration steps of BISC to be performed on the input delays. If EN_VTC is also asserted, VTC will be performed on the input delays. When updating an input or output delay in NIBBLESLICE[x] through the PL, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 0. However, when updating an input or output delay in NIBBLESLICE[x] through the RIU, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 1.
RX_RST	[5:0]	Input	ASYNC	Assert to reset RX data paths on a per-NIBBLESLICE basis. Does not reset the input delay.
T	[5:0]	Input	ASYNC	When TBYTE_CTL_x = T, T[x] is used as the tristate control signal. T is a combinatorial route and is not synchronized to the TX data.
TX_EN_VTC	[5:0]	Input	ASYNC	Assert to enable the Delay Calibration step of BISC to be performed on the output delays. If EN_VTC is also asserted, VTC will be performed on the output delays. When updating an input or output delay in NIBBLESLICE[x] through the PL, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 0. However, when updating an input or output delay in NIBBLESLICE[x] through the RIU, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 1.
TX_RST	[5:0]	Input	ASYNC	Assert to reset TX data paths on a per-NIBBLESLICE basis. Does not reset the output delay. While TX_RST[x] is asserted, the TX IOB of NIBBLESLICE[x] and the tristate control signal are set to the values of TX_INIT_x and TX_INIT_TRI, respectively.
BISC_START_OUT		Output	–	This is a simulation-only port required for BISC. If an interface is composed of multiple nibbles, connect this port to BISC_START_IN of the previous nibble in the daisy chain. If an interface is composed of only one nibble or this port is on the first nibble in the daisy chain, this port does not need to be connected anywhere.
BISC_STOP_OUT		Output	–	This is a simulation-only port required for BISC. If an interface is composed of multiple nibbles, connect this port to BISC_STOP_IN of the next nibble in the daisy chain. If an interface is composed of only one nibble or this port is on the last nibble in the daisy chain, connect this port to BISC_START_IN of the same nibble.
CLK_TO_LOWER		Output	–	Inter-byte clock output to certain numerically lower nibbles. The exception to this naming scheme is using CLK_TO_LOWER for inter-byte clocking from XPHY nibble 6 to XPHY nibble 8. In being part of inter-byte clocking, CLK_TO_LOWER can only be connected to CLK_FROM_OTHER_XPHY of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-byte clocking with each other.
CLK_TO_UPPER		Output	–	Inter-byte clock output to certain numerically higher nibbles. The exception to this naming scheme is using CLK_TO_LOWER for inter-byte clocking from XPHY nibble 6 to XPHY nibble 8. In being part of inter-byte clocking, CLK_TO_UPPER can only be connected to CLK_FROM_OTHER_XPHY of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-byte clocking with each other.
CNTVALUEOUT	[53:0]	Output	CTRL_CLK	The delay value (in taps) of the input or output delay selected by RXTX_SEL. Each NIBBLESLICE is associated with 9b of CNTVALUEOUT. NIBBLESLICE[0] is associated with CNTVALUEOUT[8:0], NIBBLESLICE[1] with CNTVALUEOUT[17:9], NIBBLESLICE[2] with CNTVALUEOUT[26:18], NIBBLESLICE[3] with CNTVALUEOUT[35:27], NIBBLESLICE[4] with CNTVALUEOUT[44:36], and NIBBLESLICE[5] with CNTVALUEOUT[53:45].
DLY_RDY		Output	ASYNC	Indicates that delay lines (input, output, quarter (QTR), and coarse (CRSE)) can now be changed. If using BISC, it also indicates that the alignment and delay calibration steps are completed. If multiple nibbles compose an interface, the assertion time for DLY_RDY can vary for each nibble. Within simulation, the assertion time of DLY_RDY will not vary for each nibble in an interface, but will vary as the XPHY configuration and connections change.
DYN_DCI	[5:0]	Output	ASYNC	DYN_DCI controls turning off/on receiver termination for NIBBLESLICE[x]. DYN_DCI can only be used with buffers that have the DCITERMDISABLE port. See Controlling IBUF_DISABLE and DYN_DCI for more information.
FIFO_EMPTY		Output	See description	Asserts when the FIFO is empty or the read and write pointers are at the same FIFO location. FIFO_EMPTY's clock domain depends upon the value of the FIFO_MODE_x attribute: When FIFO_MODE_x = ASYNC, FIFO_EMTPY is in the FIFO_RD_CLK domain When FIFO_MODE_x = SYNC, FIFO_EMPTY is in the FIFO_WR_CLK domain When FIFO_MODE_x = BYPASS, FIFO_EMPTY is always 1 See Controlling FIFO Modes for information on how FIFO_EMPTY should be controlled.
FIFO_WR_CLK		Output	–	The FIFO write clock. For source-synchronous receive interfaces with DQS_SRC = LOCAL, this is generated internally from DATAIN[0] or inter-nibble clocking. If DQS_SRC = EXTERN, FIFO_WR_CLK is generated internally from inter-byte clocking. If using serial mode, FIFO_WR_CLK is generated internally from the PLL_CLK input. See Clocking for more information.
GT_STATUS		Output	ASYNC	This port is only for memory-related use.
IBUF_DISABLE	[5:0]	Output	ASYNC	IBUF_DISABLE[x] controls disabling the receiver in NIBBLESLICE[x]. See Controlling IBUF_DISABLE and DYN_DCI for more information.
NCLK_NIBBLE_OUT		Output	–	N-clk output to certain nibbles for inter-nibble clocking. In being part of inter-nibble clocking, NCLK_NIBBLE_OUT can only be connected to NCLK_NIBBLE_IN of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-nibble clocking.
O0	[5:0]	Output	PLL_CLK	Serialized TX data to the IOB. O0[0] is the data from D0 after it has been serialized by NIBBLESLICE[0], O0[1] is the data from D1 after it has been serialized by NIBBLESLICE[1], and so on. The Controlling Tristate Control section describes how D<0-5> is serialized and output on O0, and how it changes based on data width.
PCLK_NIBBLE_OUT		Output	–	P-clk output to certain nibbles for inter-nibble clocking. In being part of inter-nibble clocking, PCLK_NIBBLE_OUT can only be connected to PCLK_NIBBLE_IN of another nibble and cannot be connected to the programmable logic. The Clocking section lists the nibbles that are capable of inter-nibble clocking.
PHY_RDY		Output	ASYNC	Indicates that the XPHY is ready for VTC. EN_VTC must be asserted for the first PHY_RDY assertion. Afterwards, if EN_VTC is deasserted, PHY_RDY will stay asserted. If EN_VTC is then reasserted, PHY_RDY will deassert and then reassert. Refer to the Controlling Built-in Self-Calibration section for VTC control.
Q0	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_0 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_0 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q0 is the word created from DATAIN[0]. The Controlling FIFO Modes section details how DATAIN[0] maps to Q0.
Q1	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_1 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_1 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q1 is the word created from DATAIN[1]. The Controlling FIFO Modes section details how DATAIN[1] maps to Q1.
Q2	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_2 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_2 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q2 is the word created from DATAIN[2]. The Controlling FIFO Modes section details how DATAIN[2] maps to Q2.
Q3	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_3 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_3 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q3 is the word created from DATAIN[3]. The Controlling FIFO Modes section details how DATAIN[3] maps to Q3.
Q4	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_4 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_4 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q4 is the word created from DATAIN[4]. The Controlling FIFO Modes section details how DATAIN[4] maps to Q4.
Q5	[7:0]	Output	FIFO_RD_CLK when FIFO_MODE_5 = ASYNC or SYNC FIFO_WR_CLK when FIFO_MODE_5 = BYPASS	Deserialized RX data from the FIFO or from bypassing the FIFO. Q5 is the word created from DATAIN[5]. The Controlling FIFO Modes section details how DATAIN[5] maps to Q5.
RIU_RD_DATA	[15:0]	Output	CTRL_CLK	Read data from the RIU
RIU_RD_VALID		Output	CTRL_CLK	Asserts when the user has control of the RIU bus. RIU writes by BISC take precedence over RIU writes from the PL. If an RIU write from the PL collides with one from BISC, RIU_RD_VALID will deassert and the PL RIU write from the cycle before RIU_RD_VALID deasserted will be stored. After BISC finishes its write(s), RIU_RD_VALID will assert and the stored PL RIU write will be executed. Any writes from the PL while RIU_RD_VALID is Low will be discarded.
T_OUT	[5:0]	Output	PLL_CLK (when TBYTE_CTL_x = PHY_WREN)/ASYNC (when TBYTE_CTL_x = T]	When TBYTE_CTL_x = T: T_OUT[x] is the T[x] input. When TBYTE_CTL_x = PHY_WREN: T_OUT[x] is the inverted and serialized PHY_WREN and is synchronous with the TX data.