Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

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AMD Versalâ„¢ devices have registers in the IOL to implement output DDR registers as in previous generations. This feature is accessed when instantiating the ODDRE1 primitive. DDR multiplexing is automatic when using the ODDRE1. No manual control of the multiplexer select is needed. This control is generated from the clock. The ODDRE1 primitive supports only the SAME_EDGE mode of operation. The SAME_EDGE mode allows designers to present both data inputs to the ODDRE1 primitive on the rising edge of the ODDRE1 clock, which saves CLB and clock resources and increases performance. The following figure shows the timing diagram of the output DDR.

Figure 1. Output DDR Timing

When using tristate control, the tristate and data paths must leverage the same registering structure. Thus, if the data path leverages the ODDRE1 block, the tristate must also leverage the ODDRE1 primitive.

Figure 2. ODDR with ODDR Serialized Tristate